DS1856E-020+ Maxim Integrated Products, DS1856E-020+ Datasheet - Page 28

• Manufacturer Part Number: DS1856E-020+
• Description: IC RES TEMP-CNTRL 20/20K 16TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of DS1856E-020+

• Taps: 256
• Resistance (ohms): 20K
• Number Of Circuits: 2
• Temperature Coefficient: 50 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.85 V ~ 5.5 V
• Operating Temperature: -40°C ~ 95°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resistance In Ohms: 20K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
A page write is initiated the same way as a byte write,
but the master does not send a STOP condition after the
first byte. Instead, after the slave acknowledges the
data byte has been received, the master can send up to
seven more bytes using the same nine-clock sequence.
The master must terminate the write cycle with a STOP
condition or the data clocked into the DS1856 will not be
latched into permanent memory.
The address counter rolls on a page during a write. The
counter does not count through the entire address
space as during a read. For example, if the starting
address is 06h and 4 bytes are written, the first byte
goes into address 06h. The second goes into address
07h. The third goes into address 00h (not 08h). The
fourth goes into address 01h. If 9 bytes or more are
written before a STOP condition is sent, the first bytes
sent are overwritten. Only the last 8 bytes of data are
written to the page.
Acknowledge Polling: Once the internally timed write
has started and the DS1856 inputs are disabled,
acknowledge polling can be initiated. The process
involves transmitting a START condition followed by the
device address. The R/W bit signifies the type of opera-
tion that is desired. The read or write sequence will only
be allowed to proceed if the internal write cycle has
completed and the DS1856 responds with a zero.
After receiving a matching address byte with the R/W bit
set high, the device goes into the read mode of opera-
tion. There are three read operations: current address
read, random read, and sequential address read.
The DS1856 has an internal address register that main-
tains the address used during the last read or write
operation, incremented by one. This data is maintained
as long as V
the last byte in memory, then the register resets to the
first address.
Once the device address is clocked in and acknowl-
edged by the DS1856 with the R/W bit set to high, the
current address data word is clocked out. The master
does not respond with a zero, but does generate a
STOP condition afterwards.
A random read requires a dummy byte write sequence to
load in the data byte address. Once the device and data
address bytes are clocked in by the master and acknowl-
edged by the DS1856, the master must generate another
START condition. The master now initiates a current
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CC
is valid. If the most recent address was
Current Address Read
Read Operations
Single Read
address read by sending the device address with the
R/W bit set high. The DS1856 acknowledges the device
address and serially clocks out the data byte.
Sequential reads are initiated by either a current
address read or a random address read. After the mas-
ter receives the first data byte, the master responds
with an acknowledge. As long as the DS1856 receives
this acknowledge after a byte is read, the master can
clock out additional data words from the DS1856. After
reaching address FFh, it resets to address 00h.
The sequential read operation is terminated when the
master initiates a STOP condition. The master does not
respond with a zero.
The following section provides a detailed description of
the 2-wire theory of operation.
The 2-wire serial-port interface supports a bidirectional
data transmission protocol with device addressing. A
device that sends data on the bus is defined as a trans-
mitter, and a device that receives data as a receiver.
The device that controls the message is called a mas-
ter. The devices that are controlled by the master are
slaves. The bus must be controlled by a master device
that generates the serial clock (SCL), controls the bus
access, and generates the START and STOP condi-
tions. The DS1856 operates as a slave on the 2-wire
bus. Connections to the bus are made through the
open-drain I/O lines SDA and SCL. The following I/O
terminals control the 2-wire serial port: SDA, SCL.
Timing diagrams for the 2-wire serial port can be found
in Figures 5 and 6. Timing information for the 2-wire
serial port is provided in the AC Electrical
Characteristics table for 2-wire serial communications.
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is
• During data transfer, the data line must remain sta-
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain high.
Start data transfer: A change in the state of the data
line from high to low while the clock is high defines a
START condition.
not busy.
ble whenever the clock line is high. Changes in the
data line while the clock line is high will be interpret-
ed as control signals.
2-Wire Serial-Port Operation
Sequential Address Read