MPC8309VMAHFCA Freescale Semiconductor, MPC8309VMAHFCA Datasheet - Page 71

417/333/233 MP Std Tmp

MPC8309VMAHFCA

Manufacturer Part Number
MPC8309VMAHFCA
Description
417/333/233 MP Std Tmp
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8309VMAHFCA

Processor Series
MPC8309
Core
e300c3
Data Bus Width
32 bit
Data Ram Size
512 MB
Interface Type
USB, CAN, UART, PCI
Maximum Clock Frequency
417 MHz
Number Of Programmable I/os
56
Operating Supply Voltage
- 0.3 V to + 1.26 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Operating Temperature Range
0 C to + 105 C
Processor To Be Evaluated
MPC8309
Supply Current (max)
5 uA
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8309VMAHFCA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
23.7
To simplify the PLL configurations, the MPC8309 might be separated into two clock domains. The first
domain contains the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and
has the csb_clk as its input clock. The second clock domain has the QUICC Engine PLL. The clock
domains are independent, and each of their PLLs is configured separately.
The following table shows suggested PLL configurations for 33 and 66 MHz input clocks.
Freescale Semiconductor
Conf No.
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
1
2
3
4
5
6
7
8
9
Suggested PLL Configurations
SPMF
0100
0010
0100
0101
0010
0100
0101
0010
0101
The VCO divider (RCWL[CEVCOD]) must be set properly so that the
QUICC Engine VCO frequency is in the range of 300–600 MHz. The
QUICC Engine frequency is not restricted by the CSB and core frequencies.
The CSB, core, and QUICC Engine frequencies should be selected
according to the performance requirements.
The QUICC Engine VCO frequency is derived from the following
equations:
qe_clk = (primary clock input × CEPMF)  (1 + CEPDF)
QUICC Engine VCO Frequency = qe_clk × VCO divider × (1 + CEPDF)
0000100
0000100
0000101
0000101
0000101
0000101
0000110
0000110
0000110
Core
PLL
Table 63. Suggested PLL Configurations
CEPMF
1001
1000
0011
0111
0111
0111
0111
0111
0111
CEDF
0
1
0
0
1
0
0
0
0
NOTE
Input Clock
Frequency
(MHz)
33.33
66.67
33.33
66.67
33.33
66.67
33.33
25
25
Frequency
133.33
133.33
133.33
133.33
133.33
133.33
166.67
(MHz)
CSB
125
125
Frequency
266.66
266.66
333.33
333.33
399.96
399.96
416.67
(MHz)
312.5
Core
375
Frequency
Engine
QUICC
(MHz)
233
233
233
225
233
233
225
233
233
Clocking
71

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