ISL22317UFRTZ Intersil, ISL22317UFRTZ Datasheet - Page 13

• Manufacturer Part Number: ISL22317UFRTZ
• Description: IC POT DGTL 128TP LN LP 10-TDFN
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL22317UFRTZ

• Taps: 128
• Resistance (ohms): 50K
• Number Of Circuits: 1
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-TDFN Exposed Pad
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Temperature Coefficient: -

Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL22317 responds with an ACK. At this time, the device
enters its standby state (see Figure 23). The non-volatile
write cycle starts after a STOP condition is determined and
requires up to 20ms delay for the next non-volatile write.
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (see Figure 24). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W bit
SIGNAL AT SDA
FROM THE
SIGNALS
MASTER
SIGNALS FROM
SDA OUTPUT FROM
SDA OUTPUT FROM
THE SLAVE
TRANSMITTER
S
A
R
T
T
SCL FROM
RECEIVER
MASTER
0
IDENTIFICATION
1
BYTE WITH
SIGNALS FROM
SIGNAL AT SDA
SIGNALS FROM
0
R/W=0
THE MASTER
1
THE SLAVE
13
0
A1
START
0
0
FIGURE 22. ACKNOWLEDGE RESPONSE FROM RECEIVER
A
C
K
0 0 0
HIGH IMPEDANCE
ADDRESS
S
A
R
T
T
BYTE
0
FIGURE 23. BYTE WRITE SEQUENCE
0
IDENTIFICATION
1
1
FIGURE 24. READ SEQUENCE
0
BYTE
1
0
A1
A
C
K
ISL22317
A
R
S
T
T
0
WRITE
0
0 1 0 1
IDENTIFICATION
A
C
K
BYTE WITH
0 0 0 0
R/W=1
ADDRESS
set to “0”, an Address Byte, a second START, and a second
Identification byte with the R/W bit set to “1”. After each of
the three bytes, the ISL22317 responds with an ACK. Then
the ISL22317 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a ACK and STOP condition) following the
last bit of the last Data Byte (see Figure 24).
In order to read back the non-volatile IVR, it is recommended
that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.
0
BYTE
A1
0
0
1
A
C
K
A
C
K
8
FIRST READ
DATA BYTE
DATA
BYTE
A
C
K
HIGH IMPEDANCE
ACK
9
A
C
K
A
C
K
S
T
O
P
LAST READ
DATA BYTE
April 15, 2010
A
C
K
FN6912.1
S
T
O
P