ISL22326WFR16Z Intersil, ISL22326WFR16Z Datasheet - Page 5

• Manufacturer Part Number: ISL22326WFR16Z
• Description: IC POT DGTL 128TP LN LP 16-QFN
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL22326WFR16Z

• Taps: 128
• Resistance (ohms): 10K
• Number Of Circuits: 2
• Temperature Coefficient: 50 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Operating Specifications
EEPROM SPECIFICATION
SERIAL INTERFACE SPECIFICATIONS
Hysteresis
SYMBOL
(Note 18)
(Note 19)
t
t
t
t
t
t
HD:STO
HD:STA
SU:DAT
HD:DAT
SU:STO
SU:STA
t
t
Cpin
t
f
HIGH
t
V
LOW
V
SCL
t
BUF
t
V
WC
t
Cb
DH
t
AA
t
t
sp
OL
D
R
F
IH
IL
Power-up Delay
EEPROM Endurance
EEPROM Retention
Non-volatile Write Cycle Time
A2, A1, A0, SHDN, SDA, and SCL
Input Buffer LOW Voltage
A2, A1, A0, SHDN, SDA, and SCL
Input Buffer HIGH Voltage
SDA and SCL Input Buffer Hysteresis
SDA Output Buffer LOW Voltage,
Sinking 4mA
A2, A1, A0, SHDN, SDA, and SCL Pin
Capacitance
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
SCL falling edge to SDA output data
valid
Time the Bus Must be Free Before the
Start of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Input Data Hold Time
STOP Condition Setup Time
STOP Condition Hold Time for Read,
or Volatile Only Write
Output Data Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive Loading of SDA or SCL
PARAMETER
5
Over the recommended operating conditions, unless otherwise specified. (Continued)
V
Register recall completed, and I
in standby state
Temperature T < +55°C
Any pulse narrower than the max spec is
suppressed
SCL falling edge crossing 30% of V
SDA exits the 30% to 70% of V
SDA crossing 70% of V
condition, to SDA crossing 70% of V
during the following START condition
Measured at the 30% of V
Measured at the 70% of V
SCL rising edge to SDA falling edge; both
crossing 70% of V
From SDA falling edge crossing 30% of V
to SCL falling edge crossing 70% of V
From SDA exiting the 30% to 70% of V
window, to SCL rising edge crossing 30% of
V
From SCL rising edge crossing 70% of V
to SDA entering the 30% to 70% of V
window
From SCL rising edge crossing 70% of V
to SDA rising edge crossing 30% of V
From SDA rising edge to SCL falling edge;
both crossing 70% of V
From SCL falling edge crossing 30% of V
until SDA enters the 30% to 70% of V
window
From 30% to 70% of V
From 70% to 30% of V
Total on-chip and off-chip
CC
CC
above Vpor, to DCP Initial Value
ISL22326
TEST CONDITIONS
CC
CC
CC
CC
CC
CC
CC
during a STOP
crossing
crossing
CC
2
C Interface
window
CC
CC
CC
CC
CC
CC
, until
CC
CC
CC
CC
CC
,
1,000,000
(Note 20)
0.05*V
0.7*V
0.1*Cb
0.1*Cb
1300
1300
1300
20 +
20 +
MIN
-0.3
600
600
600
100
600
50
10
0
0
0
CC
CC
(Note 4)
TYP
12
10
V
(Note 20)
0.3*V
CC
MAX
400
900
250
250
400
0.4
20
50
3
+ 0.3
CC
September 8, 2009
Cycles
Years
UNIT
FN6176.2
kHz
ms
ms
pF
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
V
V