MCP4341T-104E/ST Microchip Technology, MCP4341T-104E/ST Datasheet - Page 52
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MCP4341T-104E/ST
Manufacturer Part Number
MCP4341T-104E/ST
Description
IC DGTL POT QUAD 100K 20TSSOP
Manufacturer
Microchip Technology
Series
WiperLock™r
Datasheet
1.MCP4361-503EML.pdf
(80 pages)
Specifications of MCP4341T-104E/ST
Taps
129
Resistance (ohms)
100K
Number Of Circuits
4
Temperature Coefficient
150 ppm/°C Typical
Memory Type
Non-Volatile
Interface
SPI Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Resistance In Ohms
100K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
MCP434X/436X
7.5
The Write command is a 16-bit command. The Write
Command can be issued to both the Volatile and
Non-Volatile memory locations. The format of the
command is shown in
A Write command to a Volatile memory location
changes that location after a properly formatted Write
Command (16-clock) have been received.
A Write command to a Non-Volatile memory location
will only start a write cycle after a properly formatted
Write Command (16-clock) have been received and the
CS pin transitions to the inactive state (V
7.5.1
The write operation requires that the CS pin be in the
active state (V
the inactive state (V
(V
Data Byte) is then clocked in on the SCK and SDI pins.
Once all 16 bits have been received, the specified
volatile address is updated. A write will not occur if the
write command isn’t exactly 16 clocks pulses. This
protects against system issues from corrupting the
Non-Volatile memory locations.
Figure 6-2
for a single write.
FIGURE 7-2:
DS22233A-page 52
SDI
SDO
Note:
IL
). The 16-bit Write Command (Command Byte and
Note 1: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR
A
D
3
1
1
Write Data
Normal and High Voltage
and
Writes to certain memory locations will be
dependant on the state of the WiperLock
Technology bits and the Write Protect bit.
SINGLE WRITE TO VOLATILE
MEMORY
A
D
2
1
1
COMMAND BYTE
IL
or V
Figure 6-3
A
D
1
1
1
condition is cleared (the CS pin is forced to the inactive state).
IHH
IH
D
A
0
1
1
) and is driven to the active state
Figure
Write Command - SDI and SDO States.
). Typically, the CS pin will be in
0
1
1
show possible waveforms
0
1
1
7-2.
D
9
1
0
D
8
1
0
D
7
1
0
IH
).
D
6
1
0
D
5
1
0
DATA BYTE
D
4
1
0
D
3
1
0
D
2
1
0
7.5.2
The sequence to write to a single non-volatile memory
location is the same as a single write to volatile memory
with the exception that after the CS pin is driven
inactive (V
A write cycle will not start if the write command isn’t
exactly 16 clocks pulses. This protects against system
issues from corrupting the Non-Volatile memory
locations.
After the CS pin is driven inactive (V
interface may immediately be re-enabled by driving the
CS pin to the active state (V
During an EEPROM write cycle, only serial commands
to Volatile memory (addresses 00h, 01h, 04h, 05h, 06h,
07h, and 0Ah) are accepted. All other serial commands
are ignored until the EEPROM write cycle (t
pletes. This allows the Host Controller to operate on the
Volatile Wiper registers and the TCON register, and to
Read the Status Register. The EEWA bit in the Status
register indicates the status of an EEPROM Write
Cycle.
Once a write command to a Non-Volatile memory
location has been received, NO other SPI commands
should be received before the CS pin transitions to the
inactive state (V
have a Command Error (CMDERR) occur.
D
1
1
0
D
0
1 Valid Address/Command combination
0 Invalid Address/Command combination
IH
SINGLE WRITE TO NON-VOLATILE
MEMORY
), the EEPROM write cycle (t
IH
) or the current SPI command will
© 2009 Microchip Technology Inc.
IL
or V
IHH
).
IH
WC
), the serial
) is started.
wc
) com-
(1)