TDA8754HL/17/C1,51 NXP Semiconductors, TDA8754HL/17/C1,51 Datasheet - Page 37
![IC TRPL 8BIT VIDEO ADC LQFP144](/photos/6/65/66532/144-lqfp_sot486-1_pkg_sml.jpg)
TDA8754HL/17/C1,51
Manufacturer Part Number
TDA8754HL/17/C1,51
Description
IC TRPL 8BIT VIDEO ADC LQFP144
Manufacturer
NXP Semiconductors
Type
Video ADCr
Datasheet
1.TDA8754HL14C155.pdf
(57 pages)
Specifications of TDA8754HL/17/C1,51
Package / Case
144-LQFP
Resolution (bits)
8 b
Sampling Rate (per Second)
170M
Data Interface
Serial
Voltage Supply Source
Analog and Digital
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935272703518
TDA8754HL17BE-T
TDA8754HL17BE-T
TDA8754HL17BE-T
TDA8754HL17BE-T
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TDA8754HL/17/C1,51
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
Table 58:
Table 59:
Table 60:
Table 61:
Table 62:
9397 750 14984
Product data sheet
Bit
1
0
Bit
7 to 2
1
0
Bit
7 to 4
3
2
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
CLKOUTPUT - clock output register (address 1Ah) bit description
INTOSC - internal oscillator register (address 1Bh) bit allocation
INTOSC - internal oscillator register (address 1Bh) bit description
PWRMGT - power management register (address 1Eh) bit allocation
PWRMGT - power management register (address 1Eh) bit description
Symbol
OUTOSCILL
CKOENRGB
Symbol
-
SWITCHOSC
INTOSCOFF
Symbol
-
SHCKDMX
SHCKADC
9.20 Internal oscillator register
9.21 Power management register
W
X
7
-
W
X
7
-
W
X
6
-
Description
enables pin CKDATA to be switched with a multiplexer to have signal Ckdata or the internal
oscillator on the output
enables the output CKDATA to be set to high-impedance
Description
not used
enables a multiplexer to be switched; signal insertion on the input of the separator and
coast block, between the internal oscillator and pin CKEXT
disables the internal oscillator for the separator function, the coast gate and activity
detection
Description
not used
test bits; should be set to logic 0 for proper operation
test bits; should be set to logic 1 for better performances
W
X
6
-
0 = Ckdata
1 = for test
0 = active signal
1 = high-impedance
0 = normal case; if this bit is switched from logic 1 to logic 0, then an internal reset of the
coast, activity detection and sync separator is done
1 = test mode
0 = active; if this bit is switched from logic 1 to logic 0, then an internal reset of the coast,
activity detection and sync separator is done
1 = disabled
W
X
5
-
W
X
5
-
Rev. 06 — 16 June 2005
W
X
4
-
W
4
X
-
SHCKDMX
W
X
3
-
W
3
0
Triple 8-bit video ADC up to 270 Msps
…continued
SHCKADC
W
X
2
-
W
2
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SWITCHOSC INTOSCOFF
W
1
0
STBY
W
1
0
TDA8754
DVIRGB
W
0
0
W
0
0
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