TDA8754HL/17/C1,51 NXP Semiconductors, TDA8754HL/17/C1,51 Datasheet - Page 32
![IC TRPL 8BIT VIDEO ADC LQFP144](/photos/6/65/66532/144-lqfp_sot486-1_pkg_sml.jpg)
TDA8754HL/17/C1,51
Manufacturer Part Number
TDA8754HL/17/C1,51
Description
IC TRPL 8BIT VIDEO ADC LQFP144
Manufacturer
NXP Semiconductors
Type
Video ADCr
Datasheet
1.TDA8754HL14C155.pdf
(57 pages)
Specifications of TDA8754HL/17/C1,51
Package / Case
144-LQFP
Resolution (bits)
8 b
Sampling Rate (per Second)
170M
Data Interface
Serial
Voltage Supply Source
Analog and Digital
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935272703518
TDA8754HL17BE-T
TDA8754HL17BE-T
TDA8754HL17BE-T
TDA8754HL17BE-T
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TDA8754HL/17/C1,51
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
Table 45:
Table 46:
Table 47:
Table 48:
9397 750 14984
Product data sheet
Bit
7 to 5
4
3
2
1
0
Bit
7
6
5
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
VSYNCSEL - vertical sync selection register (address 14h) bit allocation
VSYNCSEL - vertical sync selection register (address 14h) bit description
CLAMP - clamp register (address 15h) bit allocation
CLAMP - clamp register (address 15h) bit description
Symbol
-
TSTCOAST
COE
VSS
COSSEL2
COSSEL1
Symbol
-
HSOSEL
CLPSEL2
9.13 Vertical sync selection register
9.14 Clamp register
W
W
X
X
7
7
-
-
HSOSEL
Description
not used
switches a multiplexer to select the output signal on pin VSYNCO
enables coast mode
enables VSYNC input signal to be inverted
selects signal for coast PLL mode
can be used for the coast PLL mode; see bit COSSEL2
Description
not used
defines the signal on the output HSYNCO; see
can be used to select the clamp signal
W
W
X
6
6
0
-
0 = output of the separator function
1 = output of the coast function
0 = coast mode
1 = no coast mode
0 = non-inverted
1 = inverted
0 = signal selected with bit COSSEL1
1 = pin coast
0 = VSYNC input
1 = VSYNC from the sync separator
0 = Hsync from the Hcounter
1 = Ckref is reference of the PLL
0 = Hsync signal generated by the pixel counter
1 = signal selected with bit CLPSEL1
CLPSEL2
W
W
X
5
5
1
-
Rev. 06 — 16 June 2005
TSTCOAST
CLPSEL1
W
W
4
0
4
0
CLPH
COE
W
W
3
0
3
0
Triple 8-bit video ADC up to 270 Msps
Section 8.3
CLPENL
VSS
W
W
2
0
2
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
COSSEL2
ICLP
W
W
1
0
1
0
TDA8754
COSSEL1
CLPT
W
W
0
0
0
0
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