AD7339BS Analog Devices Inc, AD7339BS Datasheet - Page 4

• Manufacturer Part Number: AD7339BS
• Description: IC ADC/QUAD DAC 5V W/REF 52-MQFP
• Manufacturer: Analog Devices Inc
• Type: ADC, DACr

Specifications of AD7339BS

• Rohs Status: RoHS non-compliant
• Resolution (bits): 8 b
• Sampling Rate (per Second): 2M
• Data Interface: Serial, Parallel
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 5V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-MQFP, 52-PQFP
• Converter Type: ADC/DAC
• Resolution: 8b
• Number Of Dac's: 4
• Data Rate: 2.304MSPS
• Digital Interface Type: Parallel/Serial
• Pin Count: 52
• Package Type: MQFP
• Lead Free Status / Rohs Status: Not Compliant

AD7339
TIMING CHARACTERISTICS
Parameter
ADC
t
t
t
t
t
PARALLEL DACS
t
t
t
t
t
t
t
SERIAL DACS
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Limit at
T
480
210
210
100
200
430
200
200
130
50
150
250
3.9
1.94
1.94
950
950
480
100
A
= –40 C to +85 C
Figure 2. Load Circuit for Timing Specifications
(AVDD = +5 V
OUTPUT
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
s min
s min
s min
s max
PIN
TO
10%; AGND = DGND = 0 V; T
15pF
C
L
–4–
2mA
1mA
Description
See Figure 3.
ADCCLK Period
ADCCLK Width Low
ADCCLK Width High
Data Valid After Falling Edge of ADCCLK
Data Valid Before Subsequent Falling Edge of ADCCLK
See Figure 4.
DACCLK Period
DACCLK Width Low
DACCLK Width High
Data Setup Before DACCLK Rising Edge Time
Data Hold After DACCLK Rising Edge Time
Propagation Delay
Settling Time (from 10% to 90%)
See Figure 5.
SCLK Period
SCLK Width Low
SCLK Width High
Data Setup Before SCLK Rising Edge
Latch Enable Setup Time After SCLK Falling Edge
LATCH Pulsewidth
Conversion Delay
I
I
OL
OH
+2.1V
A
= T
MlN
to T
MAX
, unless otherwise noted)
REV. 0