MAX1348BETX+T Maxim Integrated Products, MAX1348BETX+T Datasheet - Page 26

• Manufacturer Part Number: MAX1348BETX+T
• Description: IC ADC/DAC 12BIT W/FIFO 36WQFN
• Manufacturer: Maxim Integrated Products
• Type: ADC, DACr

Specifications of MAX1348BETX+T

• Resolution (bits): 12 b
• Sampling Rate (per Second): 225k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-WQFN Exposed Pad, 36-HWQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
byte load data from DIN to the GPIO configuration reg-
ister in the MAX1342/MAX1348. See Tables 13 and 14.
The register bits are updated after the last CS rising
edge. All GPIOs default to inputs upon power-up.
The data in the register controls the function of each
GPIO, as shown in Tables 13, 14, and 16.
Write the command byte 00000010 to indicate a GPIO
write operation. The eight SCLK cycles following the
command byte load data from DIN into the GPIO write
register in the MAX1342/MAX1348. See Tables 14
and 15. The register bits are updated after the last CS
rising edge.
Write the command byte 00000001 to indicate a GPIO
read operation. The eight SCLK cycles following the
command byte transfer the state of the GPIOs to DOUT
in the MAX1342/MAX1348. See Table 16.
Table 13. MAX1342/MAX1348 GPIO Configuration
Table 14. MAX1342/MAX1348 GPIO Write
Table 15. GPIO-Mode Control
Table 16. MAX1342/MAX1348 GPIO Read
26
CONFIGURATION
DIN
DOUT
DIN
DOUT
DIN
DOUT
DATA PIN
DATA PIN
DATA PIN
______________________________________________________________________________________
BIT
1
1
0
0
0
0
0
0
0
0
0
0
GPIO COMMAND BYTE
0
0
0
0
WRITE
0
0
GPIO COMMAND BYTE
GPIO COMMAND BYTE
BIT
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
OUTPUT
Tri-state
STATE
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
(open drain)
GPIO Read
GPIO Write
FUNCTION
1
0
Pulldown
Output
Output
GPIO
Input
X
0
1
0
0
0
X
0
GPIOC1
GPIOC1
0
0
X
0
Write a command byte 0001XXXX to the DAC select
register to indicate the word to follow is written to the
DAC serial interface, as detailed in Tables 1, 10, 17, and
18. Write the next 16 bits to the DAC interface register,
as shown in Tables 17 and 18. Following the high-to-low
transition of CS, the data is shifted synchronously and
latched into the input register on each falling edge of
SCLK. Each word is 16 bits. The first 4 bits are the con-
trol bits followed by 12 data bits (MSB first). See Figures
9–12 for DAC timing specifications.
If CS goes high prior to completing 16 SCLK cycles, the
command is discarded. To initiate a new transfer, drive
CS low again.
For example, writing the DAC serial interface word 1111
0000 and 0011 0100 disconnects DAC outputs 2 and 3
and forces them to a high-impedance state. DAC out-
puts 0 and 1 remain in their previous state.
X
0
GPIOC0
GPIOC0
0
0
GPIOC1
X
DATA BYTE
GPIOA1
GPIOA1
DATA BYTE
DATA BYTE
0
0
GPIOC0
X
GPIOA0
GPIOA0
0
0
GPIOA1
DAC Serial Interface
X
X
0
X
0
X
0
X
0
GPIOA0
X
0
0
X
X
X
0
X
0