MAX196BCWI+ Maxim Integrated Products, MAX196BCWI+ Datasheet - Page 11

• Manufacturer Part Number: MAX196BCWI+
• Description: IC DAS 12BIT 6CH 28-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Data Acquisition System (DAS)r

Specifications of MAX196BCWI+

• Resolution (bits): 12 b
• Sampling Rate (per Second): 100k
• Data Interface: Parallel
• Voltage Supply Source: Single Supply
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 6. Conversion Timing Using External Acquisition Mode
The MAX196/MAX198 operate with either an internal or
an external clock. Control bits (D6, D7) select either
internal or external clock mode. Once the desired clock
mode is selected, changing these bits to program
power-down will not affect the clock mode. In each
mode, internal or external acquisition can be used. At
power-up, external clock mode is selected.
Select internal clock mode to free the µP from the
burden of running the SAR conversion clock. To select
this mode, write the control byte with D7 = 0 and D6 =
1. A 100pF capacitor between the CLK pin and ground
sets this frequency to 1.56MHz nominal. Figure 7
shows a linear relationship between the internal clock
period and the value of the external capacitor used.
Select external clock mode by writing the control byte
with D7 = 0 and D6 = 0. Figure 8 shows CLK and WR
timing relationships in internal and external acquisition
modes, with an external clock. A 100kHz to 2.0MHz
external clock with 45% to 55% duty cycle is required for
proper operation. Operating at clock frequencies lower
than 100kHz will cause a voltage droop across the hold
capacitor, and subsequently degrade performance.
CS
D7–D0
INT
DOUT
WR
RD
t
CSWS
______________________________________________________________________________________
t
DS
ACQMOD = "1"
t
t
CS
WR
CONTROL
BYTE
Multirange, Single +5V, 12-Bit DAS
External Clock Mode
Internal Clock Mode
t
t
CSHW
DH
Clock Modes
t
ACQI
ACQMOD = "0"
CONTROL
BYTE
t
with 12-Bit Bus Interface
CONV
Figure 7. Internal Clock Period vs. Clock Pin Capacitance
t
D0
1500
1000
2000
500
0
t
0
CSRS
t
50
INT1
CLOCK PIN CAPACITANCE (pF)
100 150 200
DATA VALID
250
300
350
t
t
CSRH
TR
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