LTC1297DCN8 Linear Technology, LTC1297DCN8 Datasheet - Page 11

• Manufacturer Part Number: LTC1297DCN8
• Description: IC DATA ACQ SYSTEM 12BIT 8-DIP
• Manufacturer: Linear Technology
• Type: Data Acquisition System (DAS)r

Specifications of LTC1297DCN8

• Resolution (bits): 12 b
• Sampling Rate (per Second): 60k
• Data Interface: Serial, Parallel
• Voltage Supply Source: Single Supply
• Voltage - Supply: 5V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

A
The data is right- justified in the two memory locations by
rotating right twice (Figure 4). ANDing the first byte with
0F
was not included in the code. It can be inserted in the data
gathering loop or outside the loop when the data is
processed.
Interfacing to the Parallel Port of the Intel 8051 Family
The Intel 8051 has been chosen to show the interface
between the LTC1292/LTC1297 and parallel port
microprocessors. The signals CS and CLK are generated
LABEL MNEMONIC
LOOP
MC68HC11 CODE for LTC1297 Interface
PPLICATI
HEX
clears the four most significant bits. This operation
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDX
LDAB
LDAA
BCLR
NOP
NOP
NOP
STAA
ANALOG
INPUTS
O
OPERAND
#$50
$1028
#$1B
$1009
#$00
$50
#$1000
#$00
$50
$08,X,$01
$102A
U
S
Figure 4. Hardware and Software Interface to Motorola MC68HC11 Microcontroller
LTC1297
I FOR ATIO
U
COMMENTS
CONFIGURATION DATA FOR SPCR
LOAD DATA INTO SPCR ($1028)
CONFIG. DATA FOR PORT D DDR
LOAD DATA INTO PORT D DDR
LOAD DUMMY DIN WORD INTO
ACC A
LOAD DUMMY DIN DATA INTO $0
LOAD INDEX REGISTER X WITH
$1000
LOAD ACC B WITH $00
LOAD DIN INTO ACC FROM $50
D0 GOES LOW (CS GOES LOW)
3 NOP FOR t
LOAD DUMMY DIN INTO SPI,
START CLK
D
CLK
OUT
CS
W
suCS
TIMING
DO
SCK
MISO
MC68HC11
U
LOCATION #61
LOCATION #62
on two port lines and the D
line. After a falling CLK edge each data bit is loaded into the
carry bit and then rotated into the accumulator. Once the
first 8 MSBs have been shifted into the accumulator they
are loaded into register R2. The last four bits are shifted in
the same way and loaded into register R3. The output data
is left-justified in registers R2 and R3 (Figure 5).
For the LTC1297 four NOPs need to be inserted in the 8051
code after CS goes low to allow the LTC1297 to wake up
from power shutdown (t
LOOP1 LDAA
LOOP2 LDAA
LABEL MNEMONIC
D
OUT
O
B7
BPL
LDAA
STAA
STAA
BPL
BSET
LDAA
STAA
ROR
ROR
ROR
ROR
JMP
FROM LTC1297 STORED ON MC68HC11 RAM
O
B6
B5
O
$1029
LOOP1
$102A
$61
$102A
$1029
LOOP2
$08X,$01
$102A
$62
$61
$62
$61
$62
LOOP
OPERAND
B4
O
MSB
B11
B3
suCS
LTC1292/LTC1297
OUT
B10
B2
).
CHECK SPI STATUS REG
CHECK IF TRANSFER IS DONE
LOAD LTC1297 MSBs INTO ACC A
STORE MSBs IN $61
LOAD DUMMY DIN INTO SPI,
START SCK
CHECK SPI STATUS RES
CHECK IF TRANSFER IS DONE
D0 GOES HIGH (CS GOES HIGH)
LOAD LTC1297 LSBs INTO ACC A
STORE LSBs IN $62
ROTATE RIGHT WITH CARRY
NEEDED TO RIGHT JUSTIFY
THE DATA IN $61 AND $62
START NEXT CONVERSION
COMMENTS
signal is read on a third port
B1
B9
B8
B0
LTC1292/7 F04
BYTE 1
BYTE 2
11
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