LTC1292DCN8#PBF Linear Technology, LTC1292DCN8#PBF Datasheet - Page 15

• Manufacturer Part Number: LTC1292DCN8#PBF
• Description: IC DATA ACQ SYSTEM 12BIT 8-DIP
• Manufacturer: Linear Technology
• Type: Data Acquisition System (DAS)r

Specifications of LTC1292DCN8#PBF

• Resolution (bits): 12 b
• Sampling Rate (per Second): 60k
• Data Interface: Serial, Parallel
• Voltage Supply Source: Single Supply
• Voltage - Supply: 5V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Number Of Elements: 1
• Resolution: 12Bit
• Architecture: SAR
• Sample Rate: 60KSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: 5V
• Differential Input: Yes
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 5V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 500mW
• Integral Nonlinearity Error: ±0.75LSB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 8
• Package Type: PDIP N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A
t
R
settling time. In general for both the LTC1292 and LTC1297
keep the product of the total resistance and the total
capacitance less than t
met, then make C1 > 0.47 F (see RC Input Filtering
section).
suCS
SOURCE
PPLICATI
. With the minimum possible sample time of 6 s,
+ < 5k and C1 < 20pF will provide adequate
(+) INPUT
(–) INPUT
(–) INPUT
(+) INPUT
D
D
CLK
OUT
CLK
O
OUT
CS
CS
U
S
SMPL
I FOR ATIO
U
/9. If this condition can not be
(+) INPUT MUST SETTLE DURING THIS TIME
Figure 11c. Setup Time (t
t
Figure 11b. Setup Time (t
WHCS
W
HI-Z
(+) INPUT MUST SETTLE DURING THIS TIME
t
SMPL
t
WHCS
U
HI-Z
t
SMPL
suCS
suCS
) Is Not Met for the LTC1292
1ST BIT TEST (–) INPUT MUST
“–” Input Settling
At the end of the sample phase the input capacitor switches
to the “–” input and the conversion starts (see Figures 11a,
11b, 11c and 12). During the conversion, the “+” input
voltage is effectively “held” by the sample-and-hold and
will not affect the conversion result. It is critical that the
) Is Met for the LTC1292
SETTLE DURING THIS TIME
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
B11
LTC1292/LTC1297
B10
B11
LTC1292/7 F11b
LTC1292/7 F11c
B9
B10
15
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