ADC12441CIJ National Semiconductor, ADC12441CIJ Datasheet - Page 4

• Manufacturer Part Number: ADC12441CIJ
• Description: IC ADC 12BIT DYNAM TEST 28CDIP
• Manufacturer: National Semiconductor

Specifications of ADC12441CIJ

• Number Of Bits: 12
• Sampling Rate (per Second): 55k
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 70mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 28-CDIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *ADC12441CIJ

f
t
t
t
t
t
t
t
t
t
Symbol
CLK
C
A
Z
CAL
W(CAL)L
W(WR)L
ACC
0H
PD(INT)
Digital and DC Electrical Characteristics
The following specifications apply for DV
otherwise specified Boldface limits apply for T
(Notes 6 and 7) (Continued)
I
I
I
DI
AI
I
AC Electrical Characteristics
The following specifications apply for DV
Boldface limits apply for T
Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is
functional but do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed
specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test
conditions
Note 2 All voltages are measured with respect to AGND and DGND unless otherwise specified
Note 3 When the input voltage (V
5 mA The 20 mA maximum package input current rating allows the voltage at any four pins with an input current limit of 5 mA to simultaneously exceed the power
supply voltages
Symbol
OUT
SOURCE
SINK
b
CC
CC
t
1H
Clock Frequency
Clock Duty Cycle
Conversion Time
Acquisition Time
(Note 15)
Auto Zero Time
Calibration Time
Calibration Pulse Width
Minimum WR Pulse Width
Maximum Access Time
(Delay from Falling Edge of
RD to Output Data Valid)
TRI-STATE Control
(Delay from Rising Edge of
RD to Hi-Z State)
Maximum Delay from Falling Edge of
RD or WR to Reset of INT
TRI-STATE Output Leakage
Current
Output Source Current
Output Sink Current
DV
AV
V
b
CC
CC
Supply Current
Supply Current
Supply Current
Parameter
Parameter
IN
A
) at any pin exceeds the power supply rails (V
e
T
J
e
T
CC
MIN
CC
e
e
to T
AV
AV
A
MAX
V
V
V
V
f
f
f
CC
f
R
f
f
f
(Note 16)
C
R
C
CLK
CLK
CLK
CC
CLK
CLK
CLK
CLK
e
OUT
OUT
OUT
OUT
SOURCE
L
L
L
Conditions
e
e
e
e a
T
e a
e
e
e
e
e
e
e
J
all other limits T
e
e
e
e
100 pF
1 k
100 pF
Conditions
e
2 0 MHz
2 MHz CS
2 MHz CS
2 MHz CS
2 0 MHz
2 0 MHz
2 0 MHz
0V
5V
0V
5V
5 0V V
5 0V V
T
e
MIN
4
50
IN k
to T
b
b
V
e
e
e
e b
b
e b
MAX
1396(1 f
‘‘1’’
‘‘1’’
‘‘1’’
A
or V
27(1 f
26(1 f
7(1 f
(Note 9)
e
Typical
5 0V V
IN l
5 0V t
13 5
698
100
all other limits T
0 5
4 0
3 5
50
13
60
60
50
30
T
J
CLK
CLK
CLK
(AV
e
CLK
(Note 9)
Typical
REF
)
r
CC
b
)
)
25 C (Notes 6 and 7)
b
0 01
)
e
2 8
2 8
20
0 01
or DV
1
20
e a
t
f
27(1 f
7(1 f
e
CC
) the current at that pin should be limited to
5 0V and f
20 ns unless otherwise specified
A
(Notes 10 19)
26(1 f
e
CLK
(Notes 10 19)
CLK
T
Limit
706
200
200
175
2 0
J
40
60
85
90
)
b
e
)
Limit
a
b
8 0
a
CLK
3
6 0
2
6
6
CLK
25 C
3
300 ns
300 ns
)
e
2 0 MHz unless
mA (max)
mA (max)
mA (max)
MHz (max)
mA (min)
mA (min)
MHz (min)
(Limits)
% (max)
ns (max)
ns (max)
ns (max)
(Limits)
% (min)
ns (min)
ns (min)
A (max)
A (max)
Units
(max)
(max)
(max)
s (max)
Units
max
%
s
s
s