MAX1197ECM+TD Maxim Integrated Products, MAX1197ECM+TD Datasheet - Page 13

• Manufacturer Part Number: MAX1197ECM+TD
• Description: IC ADC 8BIT 60MSPS DL 48-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1197ECM+TD

• Number Of Bits: 8
• Sampling Rate (per Second): 60M
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 150mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 3. System Timing Diagram
Match the impedance of INA+ and INA-, as well as
INB+ and INB-, and set the common-mode voltage to
mid-supply (V
The full-scale range of the MAX1197 is determined by
the internally generated voltage difference between
REFP (V
The full-scale range for both on-chip ADCs is
adjustable through the REFIN pin, which is provided for
this purpose.
The MAX1197 provides three modes of reference oper-
ation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In internal reference mode, connect the internal refer-
ence output REFOUT to REFIN through a resistor (e.g.,
10kΩ) or resistor divider, if an application requires a
reduced full-scale range. For stability and noise-filtering
purposes, bypass REFIN with a >10nF capacitor to
GND. In internal reference mode, REFOUT, COM,
REFP, and REFN become low-impedance outputs.
ANALOG INPUT
DATA OUTPUT
DATA OUTPUT
CLOCK INPUT
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
DD
D7A–D0A
D7B–D0B
/2 + V
DD
/2) for optimum performance.
REFIN
Analog Inputs and Reference
______________________________________________________________________________________
Internal Reference and Parallel Outputs
/4) and REFN (V
t
DO
N - 6
N - 6
t
AD
N
Configurations
DD
N - 5
N - 5
/2 - V
N + 1
REFIN
N - 4
N - 4
/4).
5-CLOCK-CYCLE LATENCY
N + 2
t
CH
N - 3
N - 3
In buffered external reference mode, adjust the refer-
ence voltage levels externally by applying a stable and
accurate voltage at REFIN. In this mode, COM, REFP,
and REFN are outputs. REFOUT can be left open or
connected to REFIN through a >10kΩ resistor.
In unbuffered external reference mode, connect REFIN
to GND. This deactivates the on-chip reference buffers
for REFP, COM, and REFN. With their buffers shut
down, these nodes become high-impedance inputs
and can be driven through separate, external reference
sources.
For detailed circuit suggestions and how to drive this
dual ADC in buffered/unbuffered external reference
mode, see the Applications Information section.
The MAX1197’s CLK input accepts a CMOS-compati-
ble clock signal. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). In particular,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide lowest possible jitter. Any
significant aperture jitter would limit the SNR perfor-
mance of the on-chip ADCs as follows:
N + 3
N - 2
N - 2
t
CL
N + 4
N - 1
N - 1
N + 5
N
N
Clock Input (CLK)
N + 6
N + 1
N + 1
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