KAD5512HP-12Q72 Intersil, KAD5512HP-12Q72 Datasheet - Page 29

• Manufacturer Part Number: KAD5512HP-12Q72
• Description: IC ADC 12BIT 125MSPS SGL 72-QFN
• Manufacturer: Intersil
• Series: FemtoCharge™r

Specifications of KAD5512HP-12Q72

• Number Of Bits: 12
• Sampling Rate (per Second): 125M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 376mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 72-VFQFN Exposed Pad
• For Use With: KDC5512H-Q48EVAL - DAUGHTER CARD FOR KAD5512KDC5512HEVAL - DAUGHTER CARD FOR KAD5512
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NOTE:
13. At power-up, the DDR Enable bit is at a logic ‘0’ for the 72 pin package and set to a logic ‘1’ internally for the 48 pin package by an internal pull-up.
Equivalent Circuits
INP
INN
ADDR
C6-FF
(Hex)
C0
C1
C2
C3
C4
C5
AVDD
AVDD
1000O Ω
User_Patt 1_LSB
User_Patt 2_LSB
User_Patt1_MSB
User_Patt2_MSB
PARAMETER
FIGURE 41. ANALOG INPUTS
Reserved
Reserved
Test_io
NAME
Φ
F 1
Φ
F 1
29
(MSB)
BIT 7
B15
B15
User Test Mode
B7
B7
10 = Reserved
11 = Reserved
01 = Alternate
CSAMP
00 = Single
CSAMP
1.6pF
1.6pF
Φ
F 2
Φ
F 2
[1:0]
BIT 6
B14
B14
B6
B6
TABLE 16. SPI MEMORY MAP (Continued)
Φ
F 3
F 3
Φ
BIT 5
B13
B13
PIPELINE
PIPELINE
CHARGE
CHARGE
B5
B5
TO
TO
KAD5512HP
BIT 4
B12
B12
B4
B4
Reserved
Reserved
BIT 3
2 = +FS Short
3 = -FS Short
B11
B11
CLKP
CLKN
1 = Midscale
5 = reserved
6 = reserved
B3
B3
4 = Checker
0 = Off
Board
Short
Output Test Mode [3:0]
BIT 2
B10
B10
B2
B2
AVDD
AVDD
11kO
11kO
FIGURE 42. CLOCK INPUTS
7 = One/Zero Word
BIT 1
Ω
Ω
9-15 = reserved
B1
B9
B1
B9
8 = User Input
Toggle
AVDD
18kO
18kO
(LSB)
BIT 0
Ω
Ω
B0
B8
B0
B8
AVDD
VALUE
(Hex)
DEF.
00h
00h
00h
00h
00h
00h
GENERATION
October 1, 2009
INDEXED/
CLOCK-
GLOBAL
PHASE
TO
FN6808.3
G
G
G
G
G
G