KAD5512HP-12Q48 Intersil, KAD5512HP-12Q48 Datasheet - Page 8

• Manufacturer Part Number: KAD5512HP-12Q48
• Description: IC ADC 12BIT 125MSPS SGL 48-QFN
• Manufacturer: Intersil
• Series: FemtoCharge™r

Specifications of KAD5512HP-12Q48

• Number Of Bits: 12
• Sampling Rate (per Second): 125M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 376mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• For Use With: KDC5512-Q48EVAL - DAUGHTER CARD FOR KAD5512KDC5512H-Q48EVAL - DAUGHTER CARD FOR KAD5512KDC5512HEVAL - DAUGHTER CARD FOR KAD5512
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Specifications
NOTES:
10. SPI Interface timing is directly proportional to the ADC sample period (t
12. The CSB setup time increases in sleep mode due to the reduced power state, CSB setup time in Nap mode is equal to normal mode CSB setup
11. The SPI may operate asynchronously with respect to the ADC sample clock
ADC OUTPUT
Aperture Delay
RMS Aperture Jitter
Output Clock to Data Propagation Delay,
LVDS Mode
(Note 9)
Output Clock to Data Propagation Delay,
CMOS Mode
(Note 9)
Latency (Pipeline Delay)
Overvoltage Recovery
SPI INTERFACE (Notes 10, 11)
SCLK Period
SCLK Duty Cycle (t
CSB↓ to SCLK↑ Setup Time
CSB↑ after SCLK↑ Hold Time
Data Valid to SCLK↑ Setup Time
Data Valid after SCLK↑ Hold Time
Data Valid after SCLK↓ Time
Data Invalid after SCLK↑ Time
Sleep Mode CSB↓ to SCLK↑ Setup Time
(Note 12)
8. The Tri-Level Inputs internal switching thresholds are approximately 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD
9. The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data capture for most
depending on desired function.
applications. Contact factory for more info if needed.
scaled proportionally for lower sample rates.
time (4ns min).
PARAMETER
HI
/t
CLK
or t
LO
8
/t
CLK)
DDR Rising Edge
DDR Falling Edge
SDR Falling Edge
DDR Rising Edge
DDR Falling Edge
SDR Falling Edge
Write Operation
Read Operation
Read or Write
Read or Write
Read or Write
Write
Write
Read
Read
Read or Write in Sleep Mode
CONDITION
KAD5512HP
S
). Values above reflect multiples of a 4ns sample period, and must be
SYMBOL
t
t
t
t
t
t
t
DHW
DSW
t
t
t
t
t
t
OVR
DVR
DHR
CLK
CLK
DC
DC
DC
DC
DC
DC
t
t
t
t
j
L
A
A
S
H
S
-260
-160
-260
-220
-310
-310
MIN
150
16
66
25
1
3
1
3
3
TYP
375
-50
-40
-10
-90
-50
8.5
60
10
50
1
MAX
16.5
120
230
230
200
200
110
75
October 1, 2009
(Note 10)
UNITS
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
ps
ps
ps
ps
ps
ps
ps
µs
%
fs
FN6808.3