HI5762/6IN Intersil, HI5762/6IN Datasheet - Page 12

• Manufacturer Part Number: HI5762/6IN
• Description: CONV A/DDUAL 10BIT 60MSPS 44MQFP
• Manufacturer: Intersil

Specifications of HI5762/6IN

• Number Of Bits: 10
• Sampling Rate (per Second): 60M
• Data Interface: Parallel
• Number Of Converters: 8
• Power Dissipation (max): 670mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

As illustrated in the “Functional Block Diagram” on page 3
and the timing diagram in Figure 1 on page 8, eight identical
pipeline subconverter stages, each containing a two-bit flash
converter and a two-bit multiplying digital-to-analog
converter, follow the S/H circuit with the ninth stage being a
two bit flash converter. Each converter stage in the pipeline
will be sampling in one phase and amplifying in the other
clock phase. Each individual subconverter clock signal is
offset by 180° from the previous stage clock signal resulting
in alternate stages in the pipeline performing the same
operation.
The output of each of the eight identical two-bit subconverter
stages is a two-bit digital word containing a supplementary bit
to be used by the digital error correction logic. The output of
each subconverter stage is input to a digital delay line which is
controlled by the internal sampling clock. The function of the
digital delay line is to time align the digital outputs of the eight
identical two-bit subconverter stages with the corresponding
output of the ninth stage flash converter before applying the
eighteen bit result to the digital error correction logic. The
digital error correction logic uses the supplementary bits to
correct any error that may exist before generating the final ten
bit digital data output of the converter.
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus following the 6th cycle of the clock after the
analog sample is taken (see the timing diagram in Figure 1
on page 8). This time delay is specified as the data latency.
After the data latency time, the digital data representing each
succeeding analog sample is output during the following
clock cycle. The digital output data is provided in offset
binary format (see Table 1, A/D Code Table).
Internal Reference Voltage Output, V
The HI5762 is equipped with an internal reference voltage
generator, therefore, no external reference voltage is
required. V
internal reference voltage.
An internal band-gap reference voltage followed by an
amplifier/buffer generates the precision +2.5V reference
voltage used by the converter. A band-gap reference circuit is
used to generate a precision +1.25V internal reference voltage.
This voltage is then amplified by a wide-band uncompensated
operational amplifier connected in a gain-of-two configuration.
An external, user-supplied, 0.1µF capacitor connected from the
V
pole and to maintain the stability of the operational amplifier.
Reference Voltage Input, V
The HI5762 is designed to accept a +2.5V reference voltage
source at the V
converter requires V
tested with V
differential analog input voltage range of ±0.5V.
ROUT
output pin to analog ground is used to set the dominant
ROUT
RIN
RIN
connected to V
must be connected to V
input pin. Typical operation of the
RIN
to be set at +2.5V. The HI5762 is
12
REFIN
ROUT
yielding a fully
RIN
REFOUT
when using the
HI5762
The user does have the option of supplying an external +2.5V
reference voltage. As a result of the high input impedance
presented at the V
reference voltage being used is only required to source 2mA
of reference input current. In the situation where an external
reference voltage will be used an external 0.1µF capacitor
must be connected from the V
ground in order to maintain the stability of the internal
operational amplifier.
In order to minimize overall converter noise it is
recommended that adequate high frequency decoupling be
provided at the reference voltage input pin, V
Analog Input, Differential Connection
The analog input of the HI5762 is a differential input that can
be configured in various ways depending on the signal
source and the required level of performance. A fully
differential connection (Figure 16 and Figure 17) will deliver
the best performance from the converter.
Since the HI5762 is powered by a single +5V analog supply,
the analog input is limited to be between ground and +5V.
For the differential input connection this implies the analog
input common mode voltage can range from 0.25V to 4.75V.
The performance of the ADC does not change significantly
with the value of the analog input common mode voltage.
A DC voltage source, I/QV
made available to the user to help simplify circuit design
when using an AC-coupled differential input. This low output
impedance voltage source is not designed to be a reference
but makes an excellent DC bias source and stays well within
the analog input common mode voltage range over
temperature.
For the AC-coupled differential input (see Figure 16) and with
V
V
out-of-phase with V
scale when the I/Q
input is at V
the converter will be at negative full scale when the I/Q
input is equal to V
V
RIN
IN
DC
and -V
+ 0.25V (I/Q
connected to V
FIGURE 16. AC-COUPLED DIFFERENTIAL INPUT
V
-V
IN
IN
IN
DC
input signals are 0.5V
- 0.25V (I/Q
IN
DC
RIN
IN
+ - I/Q
IN
ROUT
+ input is at V
- 0.25V and I/Q
. The converter will be at positive full
input pin, 1.25kΩ typically, the external
IN
, full scale is achieved when the
DC
IN
- = -0.5V).
+ - I/Q
, equal to 3.0V (typical), is
R
ROUT
R
DC
P-P
IN
IN
output pin to analog
- = +0.5V). Conversely,
+ 0.25V and the I/Q
, with -V
- is at
I/QV
I/Q
I/Q
IN
IN
HI5762
IN
RIN
DC
-
+
January 22, 2010
being 180°
.
IN
FN4318.3
+
IN
-