ADC12020CIVY National Semiconductor, ADC12020CIVY Datasheet - Page 19

• Manufacturer Part Number: ADC12020CIVY
• Description: IC ADC 12BIT 20MSPS 32-LQFP
• Manufacturer: National Semiconductor

Specifications of ADC12020CIVY

• Number Of Bits: 12
• Sampling Rate (per Second): 20M
• Number Of Converters: 1
• Power Dissipation (max): 227mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *ADC12020CIVY

4.0 POWER SUPPLY CONSIDERATIONS
The power supply pins should be bypassed with a 10 µF ca-
pacitor and with a 0.1 µF ceramic chip capacitor within a
centimeter of each power pin. Leadless chip capacitors are
preferred because they have low series inductance.
As is the case with all high-speed converters, the ADC12020
is sensitive to power supply noise. Accordingly, the noise on
the analog supply pin should be kept below 100 mV
No pin should ever have a voltage on it that is in excess of the
supply voltages, not even on a transient basis. Be especially
careful of this during turn on and turn off of power.
The V
operated from a supply in the range of 2.35V to V
5V). This can simplify interfacing to 3V devices and systems.
DO NOT operate the V
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essen-
tial to ensure accurate conversion. Maintaining separate ana-
log and digital areas of the board, with the ADC12020
between these areas, is required to achieve specified perfor-
mance.
The ground return for the data outputs (DR GND) carries the
ground current for the output drivers. The output current can
exhibit high transients that could add noise to the conversion
process. To prevent this from happening, the DR GND pins
should NOT be connected to system ground in close proximity
to any of the ADC12020's other ground pins.
DR
pin provides power for the output drivers and may be
DR
pin at a voltage higher than V
FIGURE 6. Driving the Signal Inputs with a Transformer
D
(nominal
P-P
.
D
.
19
Capacitive coupling between the typically noisy digital circuit-
ry and the sensitive analog circuitry can lead to poor perfor-
mance. The solution is to keep the analog circuitry separated
from the digital circuitry, and to keep the clock line as short as
possible.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have signif-
icant impact upon system noise performance. The best logic
family to use in systems with A/D converters is one which
employs non-saturating transistor designs, or has low noise
characteristics, such as the 74LS, 74HC(T) and 74AC(T)Q
families. The worst noise generators are logic families that
draw the largest supply current transients during clock or sig-
nal edges, like the 74F and the 74AC(T) families. In high
speed circuits, however, it is often necessary to use these
higher speed devices. Best performance requires careful at-
tention to PC board layout and to proper signal integrity
techniques.
The effects of the noise generated from the ADC output
switching can be minimized through the use of 47Ω to 100Ω
resistors in series with each data output line. Locate these
resistors as close to the ADC output pins as possible.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
Generally, analog and digital lines should cross each other at
90° to avoid crosstalk. To maximize accuracy in high speed,
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