ADC12020CIVY National Semiconductor, ADC12020CIVY Datasheet - Page 16

• Manufacturer Part Number: ADC12020CIVY
• Description: IC ADC 12BIT 20MSPS 32-LQFP
• Manufacturer: National Semiconductor

Specifications of ADC12020CIVY

• Number Of Bits: 12
• Sampling Rate (per Second): 20M
• Number Of Converters: 1
• Power Dissipation (max): 227mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *ADC12020CIVY

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Functional Description
Operating on a single +5V supply, the ADC12020 uses a
pipeline architecture and has error correction circuitry to help
ensure maximum performance. The differential analog input
signal is digitized to 12 bits.
The reference input is buffered to ease the task of driving that
pin. The output word rate is the same as the clock frequency.
The analog input voltage is acquired at the rising edge of the
clock and the digital data for a given sample is delayed by the
pipeline for 6 clock cycles.
A logic high on the power down (PD) pin reduces the con-
verter power consumption to 40 mW.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC12020:
1.1 Analog Inputs
The ADC12020 has two analog signal inputs, V
These two pins form a differential input pair. There is one ref-
erence input pin, V
1.2 Reference Pins
The ADC12020 is designed to operate with a 2.0V reference,
but performs well with reference voltages in the range of 1.0V
to 2.4V. Lower reference voltages will decrease the signal-to-
noise ratio (SNR). Increasing the reference voltage (and the
input signal swing) beyond 2.4V will degrade THD for a full-
scale input.
It is very important that all grounds associated with the refer-
ence voltage and the input signal make connection to the
ground plane at a single point to minimize the effects of noise
currents in the ground path.
The three Reference Bypass Pins (V
made available for bypass purposes. These pins should each
be bypassed to ground with a 0.1 µF capacitor. Smaller ca-
pacitor values will allow faster recovery from the power down
mode, but may result in degraded noise performance. DO
NOT LOAD these pins.
1.3 Signal Inputs
The signal inputs are V
defined as
Figure 2 shows the expected input signal range.
Note that the common mode input voltage range is 1V to 3V
with a nominal value of V
between ground and 4V.
The Peaks of the individual input signals (V
should each never exceed the voltage described as
to maintain THD and SINAD performance.
4.75V
V
2.35V
100 kHz
1.0V
1.0V
D
= V
≤
≤
≤
≤
A
V
V
V
V
≤
REF
CM
A
DR
f
CLK
≤
≤
≤
≤
5.25V
4.0V
2.4V
V
≤
V
REF
D
IN
30 MHz
V
+, V
IN
.
IN
= (V
A
+ and V
IN
/2. The input signals should remain
− = V
IN
+) – (V
REF
IN
−. The input signal, V
+ V
IN
RP
−)
CM
, V
RM
IN
and V
IN
+ and V
+ and V
RN
) are
IN
IN
IN
, is
−)
−.
16
The ADC12020 performs best with a differential input with
each input centered around V
swing at both V
of the reference voltage or the output data will be clipped. The
two input signals should be exactly 180° out of phase from
each other and of the same amplitude. For single frequency
inputs, angular errors result in a reduction of the effective full
scale input. For a complex waveform, however, angular errors
will result in distortion.
For angular deviations of up to 10 degrees from these two
signals being 180 out of phase, the full scale error in LSB can
be described as approximately
Where dev is the angular difference, in degrees, between the
two signals having a 180° relative phase relationship to each
other (see Figure 3). Drive the analog inputs with a source
impedance less than 100Ω.
FIGURE 3. Angular Errors Between the Two Input Signals
For differential operation, each analog input signal should
have a peak-to-peak voltage equal to the input reference volt-
age, V
V
TABLE 1. Input to Output Relationship—Differential Input
CM
V
V
V
V
.
CM
CM
CM
CM
REF
V
− V
− V
V
+ V
+ V
FIGURE 2. Expected Input Signal Range
CM
, and be centered around a common mode voltage,
IN
+
REF
REF
REF
REF
E
Will Reduce the Output Level
IN
/2
/4
/4
/2
FS
+ and V
= 4096 ( 1 - sin (90° + dev))
V
V
V
V
IN
CM
CM
CM
CM
− each should not exceed the value
+ V
+ V
V
− V
− V
V
IN
CM
CM
−
REF
REF
REF
REF
. The peak-to-peak voltage
/2
/4
/4
/2
20051712
20051711
0000 0000 0000
0100 0000 0000
1000 0000 0000
1100 0000 0000
1111 1111 1111
Output