AD7856KR-REEL Analog Devices Inc, AD7856KR-REEL Datasheet
AD7856KR-REEL
Specifications of AD7856KR-REEL
Related parts for AD7856KR-REEL
AD7856KR-REEL Summary of contents
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FEATURES Single 5 V Supply 285 kSPS Throughput Rate Self- and System Calibration with Autocalibration on Power-Up Eight Single-Ended or Four Pseudo-Differential Inputs Low Power Typ Automatic Power-Down After Conversion (2.5 W Typ) Flexible Serial Interface: 8051/SPI™/QSPI™/ ...
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AD7856–SPECIFICATIONS = 4.096 V External Reference unless otherwise noted, SLEEP = Logic High; T REF /REF IN OUT tions apply for Mode 2 operation, standard 3-wire SPI interface; refer to Detailed Timing section for Mode 1 Specifications. Parameter DYNAMIC PERFORMANCE ...
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Parameter POWER PERFORMANCE Normal Mode 6 Sleep Mode With External Clock On With External Clock Off Normal Mode Power Dissipation Sleep Mode Power Dissipation With External Clock On With External Clock Off SYSTEM ...
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AD7856 1 TIMING SPECIFICATIONS Limit MIN MAX Parameter A Version K Version 2 f 500 500 CLKIN SCLK 3 t 100 100 3.5 5.25 CONVERT ...
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TYPICAL TIMING DIAGRAMS Figures 2 and 3 show typical read and write timing diagrams for serial Interface Mode 2. The reading and writing occurs after conversion in Figure 2, and during conversion in Figure 3. To attain the maximum sample ...
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... Although the AD7856 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Model AD7856AN + 0 AD7856AR + 0 AD7856KR + 0 AD7856ARS + 0 EVAL-AD7856CB . . . . . . . 10 mA EVAL-CONTROL BOARD ...
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Pin Mnemonic Description CONVST 1 Convert Start. Logic Input. A low to high transition on this input puts the track/hold into its hold mode and starts conversion. When this input is not used, it should be tied to DV Busy ...
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AD7856 1 TERMINOLOGY Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The end- points of the transfer function are zero scale, a point 1/2 LSB below the first ...
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ON-CHIP REGISTERS The AD7856 powers up with a set of default conditions. The only writing that is required is to select the channel configuration. Without performing any other write operations the AD7856 still retains the flexibility for performing a full ...
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AD7856 CONTROL REGISTER The arrangement of the Control Register is shown below. The control register is a write only register and contains 14 bits of data. The control register is selected by putting two 1s in ADDR1 and ADDR0. The ...
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SGL/DIFF *AIN(+) refers to the positive input seen by the AD7856 sample and hold circuit. AIN(–) refers to the negative input seen by the ...
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AD7856 STATUS REGISTER The arrangement of the Status Register is shown below. The status register is a read only register and contains 16 bits of data. The status register is selected by first writing to the control register and putting ...
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CALIBRATION REGISTERS The AD7856 has ten calibration registers in all, eight for the DAC, one for the offset and one for gain. Data can be written to or read from all ten calibration registers. In self- and system calibration the ...
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AD7856 START WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1, RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11 CAL REGISTER POINTER IS AUTOMATICALLY RESET READ CAL REGISTER CAL REGISTER POINTER IS AUTOMATICALLY INCREMENTED LAST ...
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CIRCUIT INFORMATION The AD7856 is a fast, 14-bit single supply A/D converter. The part requires an external 6 MHz/4 MHz master clock (CLKIN), capacitors, a CONVST signal to start conversion and two C REF power supply decoupling capacitors. The part ...
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AD7856 ANALOG INPUT The equivalent circuit of the analog input section is shown in Figure 11. During the acquisition interval the switches are both in the track position and the AIN(+) charges the 20 pF capaci- resistance. On the rising ...
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TRACK AND HOLD AIN(+) AMPLIFIER REF AIN(–) Figure 14 Input Configuration REF Transfer Function For the AD7856 input range the designed code transitions occur midway between successive integer LSB values (i.e., ...
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AD7856 PERFORMANCE CURVES The following performance curves apply to Mode 2 operation only conversion is initiated in software, then a slight degra- dation in SNR can be expected when in Mode 2 operation. As the sampling instant cannot ...
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A combination of hardware and software selection can also be used to achieve the desired effect. Table VI. Power Management Options SLEEP PMGT1 PMGT0 Bit Bit Pin Comment Full Power-Down Between Conversions (HW/SW Full ...
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AD7856 The AD7856 powers up from a full hardware or software power-down typ. This limits the throughput which the part is capable kSPS for the K grade and 113 kSPS for the A grade ...
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THROUGHPUT – kSPS Figure 24. Power vs. Throughput Rate (6 MHz CLK) CALIBRATION SECTION Calibration Overview The automatic calibration that is performed on power up en- sures that the calibration options covered in ...
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AD7856 is initiated. Typical figures are given in Table VIII. The timing diagrams for the other self-calibration options will be similar to that outlined in Figure 25 100ns MIN 2 250026 CAL ...
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There will never be any need to perform more than three system (offset + gain) calibrations. The zero scale error is adjusted for an offset ...
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AD7856 Table X. Interface Mode Description Interface Processor/ Mode Controller 1 8XC51 8XL51 PIC17C42 2 68HC11 68L11 68HC16 PIC16C64 ADSP-21xx DSP56000 DSP56001 DSP56002 DSP56L002 DETAILED TIMING SECTION Mode 1 (2-Wire 8051 Interface) The read and write takes place on the ...
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Mode 2 (3-Wire SPI/QSPI Interface Mode) This is the DEFAULT INTERFACE MODE. In Figure 33 below we have the timing diagram for interface Mode 2, which is the SPI/QSPI interface mode. Here the SYNC input is active low and may ...
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AD7856 CONFIGURING THE AD7856 The AD7856 contains 14 on-chip registers that can be accessed via the serial interface. In the majority of applications it will not be necessary to access all of these registers. Here the CLKIN signal is applied ...
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Interface Mode 2 Configuration Figure 35 shows the flowchart for configuring the part in Inter- face Mode 2. In this case the read and write operations take place simultaneously via the serial port. Writing all 0s ensures WAIT 150ms FOR ...
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AD7856 MICROPROCESSOR INTERFACING In many applications, the user may not require the facility of writing to most of the on-chip registers. The only writing neces- sary is to set the input channel configuration. After this the CONVST is applied, a ...
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OPTIONAL 4MHz/6MHz DV 68HC11/L11/16 DD SPI SS HC16, QSPI SCK MASTER MISO OPTIONAL IRQ MOSI Figure 38. 68HC11 and 68HC16 Interface AD7856 to ADSP-21xx Interface Figure 39 shows the AD7856 interface to the ADSP-21xx. The ADSP-21xx is the master and ...
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AD7856 Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7856 to avoid noise coupling. The power supply lines to the AD7856 should ...
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PAGE INDEX Topic FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AD7856 0.210 (5.33) MAX 0.200 (5.05) 0.125 (3.18) 0.0118 (0.30) 0.0040 (0.10) 0.078 (1.98) 0.068 (1.73) 0.008 (0.203) 0.002 (0.050) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Plastic DIP (N-24) 1.275 (32.30) 1.125 (28.60 0.280 (7.11) ...