AD7731BR-REEL7 Analog Devices Inc, AD7731BR-REEL7 Datasheet - Page 29

• Manufacturer Part Number: AD7731BR-REEL7
• Description: IC ADC 24BIT SIGMA-DELTA 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7731BR-REEL7

• Rohs Status: RoHS non-compliant
• Number Of Bits: 24
• Sampling Rate (per Second): 6.4k
• Data Interface: DSP, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 125mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• For Use With: EVAL-AD7731EBZ - BOARD EVALUATION FOR AD7731

CALIBRATION
The AD7731 provides a number of calibration options that can
be programmed via the MD2, MD1 and MD0 bits of the Mode
Register. The different calibration options are outlined in the
Mode Register and Calibration Operations sections. A calibra-
tion cycle may be initiated at any time by writing to these bits of
the Mode Register. Calibration on the AD7731 removes offset
and gain errors from the device.
The AD7731 gives the user access to the on-chip calibration
registers allowing the microprocessor to read the device’s cali-
bration coefficients and also to write its own calibration coeffi-
cients to the part from prestored values in E
the microprocessor much greater control over the AD7731’s
calibration procedure. It also means that by comparing the
coefficients after calibration with prestored values in E
the user can verify that the device has correctly performed its
calibration. The values in these calibration registers are 24 bits
wide. In addition, the span and offset for the part can be ad-
justed by the user.
Internally in the AD7731, the coefficients are normalized before
being used to scale the words coming out of the digital filter.
The offset calibration register contains a value which, when
normalized, is subtracted from all conversion results. The gain
calibration register contains a value which, when normalized, is
multiplied by all conversion results. The offset calibration coeffi-
cient is subtracted from the result prior to the multiplication by
the gain coefficient.
The AD7731 offers self-calibration or system calibration facili-
ties. For full calibration to occur on the selected channel, the
on-chip microcontroller must record the modulator output for
two different input conditions. These are “zero-scale” and “full-
scale” points. These points are derived by performing a conver-
sion on the different input voltages provided to the input of the
modulator during calibration. The result of the “zero-scale”
calibration conversion is stored in the Offset Calibration Regis-
ter for the appropriate channel. The result of the “full-scale”
calibration conversion is stored in the Gain Calibration Register
for the appropriate channel. With these readings, the micro-
controller can calculate the offset and the gain slope for the
input-to-output transfer function of the converter. Internally,
the part works with 33 bits of resolution to determine its conver-
sion result of either 16 bits or 24 bits.
The sequence in which the zero-scale and full-scale calibration
occurs depends upon the type of full-scale calibration being
performed. The internal full-scale calibration is a two-step cali-
bration that alters the value of the Offset Calibration Register.
Thus, the user must perform a zero-scale calibration (either
internal or system) after an internal full-scale calibration to
correct the Offset Calibration Register contents. When using
system full-scale calibration, it is recommended that the zero-
scale calibration (either internal or system) is performed first.
Calibration time is the same regardless of whether the SKIP
mode is enabled or not. This is because the SKIP bit is ignored
and the second stage filter is included in the calibration cycle.
This is done to derive more accurate calibration coefficients. If
the subsequent operating mode is with CHP = 0, the calibration
should be performed with CHP = 0 so the offset calibration
coefficient and the subsequent conversion offsets are consistent.
Since the calibration coefficients are derived by performing a
REV. 0
REV. A
2
PROM. This gives
2
PROM,
–29–
conversion on the input voltage provided, the accuracy of the
calibration can only be as good as the noise level which the part
provides in normal mode. To optimize the calibration accuracy,
it is recommended to calibrate the part at its lowest output rate
where the noise level is lowest. The coefficients generated at any
output update rate will be valid for all selected output update
rates. This scheme of calibrating at the lowest output update
rate does mean that the duration of calibration is longer.
Internal Zero-Scale Calibration
An internal zero-scale calibration is initiated on the AD7731 by
writing the appropriate values (1, 0, 0) to the MD2, MD1 and
MD0 bits of the Mode Register. In this calibration mode with a
unipolar input range, the zero-scale point used in determining
the calibration coefficients is with the inputs of the differential
pair internally shorted on the part (i.e., AIN[+] = AIN[–] =
Externally-Applied AIN[–] voltage). The PGA is set for the
selected gain (as per the RN2, RN1, RN0 bits in the Mode
Register) for this internal zero-scale calibration conversion.
The duration time of the calibration depends upon the CHP bit
of the Filter Register. With CHP = 1, the duration is 22 1/
Output Rate; with CHP = 0, the duration is 24 1/Output
Rate. At this time the MD2, MD1 and MD0 bits in the Mode
Register return to 0, 0, 0 (Sync or Idle Mode for the AD7731).
The RDY line goes high when calibration is initiated and re-
turns low when calibration is complete. Note, the part has not
performed a conversion at this time; it has simply performed a
zero-scale calibration and updated the Offset Calibration
Register for the selected channel. The user must write either
0, 0, 1 or 0, 1 ,0 to the MD2, MD1, MD0 bits of the Mode
Register to initiate a conversion. If RDY is low before (or goes
low during) the calibration command write to the Mode Regis-
ter, it may take up to one modulator cycle (MCLK IN/16) be-
fore RDY goes high to indicate that calibration is in progress.
Therefore, RDY should be ignored for up to one modulator
cycle after the last bit of the calibration command is written to
the Mode Register.
For bipolar input ranges in the internal zero-scale calibrating
mode, the sequence is very similar to that just outlined. In this
case, the zero-scale point is exactly the same as above but since
the part is configured for bipolar operation, the output code for
zero differential input is 800000 Hex in 24-bit mode.
The internal zero-scale calibration needs to be performed as one
part of a two-step full calibration. However, once a full cali-
bration has been performed, additional internal zero-scale
calibrations can be performed by themselves to adjust the
part’s zero-scale point only. When performing a two-step full
calibration, care should be taken as to the sequence in which the
two steps are performed. If the internal zero-scale calibration is
one part of a full self-calibration, then it should take place after
an internal full-scale calibration. If it takes place in association
with a system full-scale calibration, then this internal zero-scale
calibration should be performed first.
AD7731