AD7997BRUZ-0 Analog Devices Inc, AD7997BRUZ-0 Datasheet - Page 23

IC ADC 10BIT 8CHAN I2C 20TSSOP

AD7997BRUZ-0

Manufacturer Part Number
AD7997BRUZ-0
Description
IC ADC 10BIT 8CHAN I2C 20TSSOP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD7997BRUZ-0

Data Interface
I²C, Serial
Number Of Bits
10
Sampling Rate (per Second)
188k
Number Of Converters
1
Power Dissipation (max)
2.2mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP (0.173", 4.40mm Width)
Resolution (bits)
10bit
Sampling Rate
188kSPS
Input Channel Type
Single Ended
Supply Voltage Range - Analog
2.7V To 5.5V
Supply Current
1.4mA
Number Of Elements
1
Resolution
10Bit
Architecture
SAR
Sample Rate
188KSPS
Input Polarity
Unipolar
Input Type
Voltage
Rated Input Volt
2.5V
Differential Input
No
Power Supply Requirement
Single
Single Supply Voltage (typ)
3.3/5V
Single Supply Voltage (min)
2.7V
Single Supply Voltage (max)
5.5V
Dual Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Power Dissipation
6.05mW
Differential Linearity Error
±0.5LSB
Integral Nonlinearity Error
±0.5LSB
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
20
Package Type
TSSOP
Input Signal Type
Single-Ended
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-AD7997CBZ - BOARD EVALUATION AD7997
Lead Free Status / Rohs Status
Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD7997BRUZ-0
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD7997BRUZ-0REEL
Quantity:
15 000
SERIAL INTERFACE
Control of the AD7997/AD7998 is carried out via the I
compatible serial bus. The devices are connected to this bus as
slave devices under the control of a master device, such as the
processor.
SERIAL BUS ADDRESS
Like all I
7-bit serial address. The 3 MSBs of this address for the AD7997/
AD7998 are set to 010. The AD7997/AD7998 come in two
versions, the AD7997-0/AD7997-0 and AD7997-1AD7998-1.
The two versions have three different I
which are selected by either tying the address select pin, AS, to
AGND or V
different addresses for the two versions, up to five AD7997/
AD7998 devices can be connected to a single serial bus, or the
addresses can be set to avoid conflicts with other devices on the
bus. (See Table 6.)
The serial bus protocol operates as follows.
The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line SDA, while the serial clock line, SCL, remains high.
This indicates that an address/data stream follows. All slave
peripherals connected to the serial bus responds to the start
condition and shift in the next eight bits, consisting of a
7-bit address (MSB first) plus an R/ W bit that determines the
direction of the data transfer, that is, whether data is written to
or read from the slave device.
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the acknowledge
bit. All other devices on the bus remain idle while the selected
device waits for data to be read from or written to it. If the R/ W
bit is a 0, the master writes to the slave device. If the R/ W bit is a
1, the master reads from the slave device.
2
C-compatible devices, the AD7997/AD7998 have a
DD
, or by letting the pin float (see Table 6). By giving
2
C addresses available,
2
C-
Rev. 0 | Page 23 of 32
Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an acknowledge bit from
the receiver of data. Transitions on the data line must occur
during the low period of the clock signal and remain stable
during the high period because a low-to-high transition when
the clock is high may be interpreted as a stop signal.
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the 10th clock pulse to assert a stop condition. In
read mode, the master device pulls the data line high during the
low period before the ninth clock pulse. This is known as No
Acknowledge. The master then takes the data line low during
the low period before the 10th clock pulse, then high during the
10th clock pulse to assert a stop condition.
Any number of bytes of data may be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation, because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
AD7997/AD7998

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