TC850CLW Microchip Technology, TC850CLW Datasheet - Page 17

• Manufacturer Part Number: TC850CLW
• Description: IC ADC 15BIT FAST 44PLCC
• Manufacturer: Microchip Technology

Specifications of TC850CLW

• Data Interface: Parallel
• Number Of Bits: 15
• Sampling Rate (per Second): 40
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Resolution (bits): 15bit
• Sampling Rate: 40SPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: ± 5V
• Supply Current: 2mA
• Digital Ic Case Style: LCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8-3 shows a typical interface to a μP I/O port or
single-chip μC. The TC850 operates in the Continuous
mode and can either interrupt the μC/μP or be polled
with an input pin.
FIGURE 8-3:
Port or Single Chip
Since the PA0-PA7 inputs are dedicated to reading A/D
data, the A/D CS/CE inputs can be enabled continu-
ously. In Continuous mode, data must be read in 3
bytes, as shown in Table 6-1. The required RD pulses
are provided by a μC/μP output pin.
The circuit of Figure 8-3 can also operate in the
Demand mode, with the start-up conversion strobe
generated by a μC/μP output pin. In this case, the L/H
and CONT/DEMAND inputs can be controlled by I/O
pins and the RD input connected to digital ground.
© 2006 Microchip Technology Inc.
CONT/DEMAND
CE
WR
NC
BUSY
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
RD
CS
μ
Interface to Typical
C
TC850
+5V
INTERRUPT
PB0
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
mC OR mP
I/O PORT
μ
P I/O
8.3
When CONT/DEMAND input is LOW, the TC850
performs a conversion each time CE and CS are active
and WR is strobed LOW.
The Demand mode conversion timing is shown in
Figure 8-1. BUSY goes LOW and data is valid 1155
clock pulses after WR goes LOW. After BUSY goes
low, 125 additional clock cycles are required before the
next conversion cycle will begin.
Once conversion is started, WR is ignored for 1100
internal clock cycles. After 1100 clock cycles, another
WR pulse is recognized and initiates a new conversion
when the present conversion is complete. A negative
edge on WR is required to begin conversion. If WR is
held LOW, conversions will not occur continuously.
The A/D conversion data is valid on the falling edge of
BUSY and remains valid until one-half internal clock
cycle before BUSY goes HIGH on the succeeding
conversion. BUSY can be monitored with an I/O pin to
determine end of conversion or to generate a μP
interrupt.
In Demand mode, the three data bytes can be read in
any desired order. The TC850 is simply regarded as
three bytes of memory and accessed accordingly. The
bus output timing is shown in Figure 8-2.
8.4
When the CONT/DEMAND input is HIGH, the TC850
performs conversions continuously. Data will be valid
on the falling edge of BUSY and all three bytes must be
read within 443-1/2 internal clock cycles of BUSY going
LOW. The timing diagram is shown in Figure 8-3.
In Continuous mode, OVR/POL and L/H byte-select
inputs are ignored. The TC850 automatically cycles
through three data bytes, as shown in Table 6-1. Bus
output timing in the Continuous mode is shown in
Figure 8-4.
Demand Mode Interface Timing
Continuous Mode Interface Timing
DS21479C-page 17
TC850