LTC1278-4CSW Linear Technology, LTC1278-4CSW Datasheet - Page 8

• Manufacturer Part Number: LTC1278-4CSW
• Description: IC A/DCONV SAMPLNG W/SHTDN24SOIC
• Manufacturer: Linear Technology

Specifications of LTC1278-4CSW

• Number Of Bits: 12
• Sampling Rate (per Second): 400k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 150mW
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LTC1278-4CS

TI I G DIAGRA S
LTC1278
TEST CIRCUITS
CONVERSION DETAILS
The LTC1278 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of conversion the successive approxi-
mation register (SAR) is reset. Once a conversion cycle
has begun it cannot be restarted.
During conversion, the internal 12-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, the A
capacitor during the acquire phase, and the comparator
8
APPLICATIONS
RD
CS
DBN
W U
CS to RD Setup Timing
A) HIGH-Z TO V
t
1
AND V
3k
DGND
OL
Load Circuits for Access Timing
IN
TO V
input connects to the sample-and-hold
OH
OH
U
(t
8
(t
)
6
C
)
LTC1278 • TC01
L
INFORMATION
U
W
DBN
W
B) HIGH-Z TO V
AND V
CONVST
OH
5V
CS
TO V
3k
CS to CONVST Setup Timing
DGND
C
OL
LTC1278 TA08
L
U
OL
(t
8
(t
)
6
)
t
2
offset is nulled by the feedback switch. In this acquire
phase, a minimum delay of 200ns will provide enough
time for the sample-and-hold capacitor to acquire the
analog signal. During the convert phase, the comparator
feedback switch opens, putting the comparator into the
DBN
A
IN
LTC1278 • TC02
SAMPLE
HOLD
A) V
3k
Load Circuits for Output Float Delay
OH
DGND
TO HIGH-Z
C
SAMPLE
C
V
DAC
DAC
Figure 1. A
CONVST
10pF
DAC
SHDN to CONVST Wake-Up Timing
SHDN
IN
Input
SAMPLE
–
+
DBN
COMPARATOR
t
SI
3
B) V
OL
TO HIGH-Z
5V
LTC1278 F1
12-BIT
LATCH
3k
DGND
10pF
R
S
A
1278 • TA08
LTC1278 • TC03