LTC1402CGN Linear Technology, LTC1402CGN Datasheet - Page 16

• Manufacturer Part Number: LTC1402CGN
• Description: IC ADC 12BIT 2.2MSPS SHDN 16SSOP
• Manufacturer: Linear Technology

Specifications of LTC1402CGN

• Number Of Bits: 12
• Sampling Rate (per Second): 2.2M
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 150mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC1402
APPLICATIONS
15mW. The internal reference remains powered in Nap
mode. One or more rising edges at SCK wake up the
LTC1402 for service very quickly, and CONV can start an
accurate conversion within a clock cycle. Four rising edges
at CONV, without any intervening rising edges at SCK, put
the LTC1402 in Sleep mode and the power drain drops
from 90mW to 10 W. One or more rising edges at SCK
wake up the LTC1402 for operation. The internal reference
(V
the REFREADY bit in the D
10ms to go high after the reference output Pin 5 (V
finished slewing. Note that, using sleep mode more fre-
quently than every 2ms, compromises the settled accu-
racy of the internal reference. Figure 12 shows the power
consumption versus the conversion rate. Note that, for
slower conversion rates, the Nap and Sleep modes can be
used for substantial reductions in power consumption.
DIGITAL INTERFACE
The LTC1402 has a 3-wire SPI (Serial Protocol Interface)
interface. The SCK and CONV inputs and D
implement this interface. The SCK and CONV inputs are TTL
compatible and also accept swings from 3V or 5V logic. The
amplitude of D
swings by tying the independent output supply OV
(Pin 11) to the same supply as system logic. A detailed de-
scription of the three serial port signals follows.
16
REF
) takes 2ms to slew and settle with a 10 F load, and
Figure 12. Power Consumption vs Sample Rate
in Normal Mode, Nap Mode and Sleep Mode
0.001
0.01
100
0.1
10
1
0.01
OUT
V
SS
can easily produce 5V logic or 3V logic
V
V
DUAL 5V
U
SINGLE 5V
DD
DD
CURRENT
V
SLEEP MODE
SINGLE 5V
CURRENT
DD
CURRENT
SAMPLE RATE (MHz)
CURRENT
0.1
INFORMATION
U
OUT
V
NAP MODE
stream takes an additional
DD
CURRENT
V
DUAL 5V
1
W
SS
CURRENT
1402 F12
10
OUT
U
REF
output
) has
DD
CONV at Pin 16
The rising edge of CONV starts a conversion but subse-
quent rising edges at CONV, during the following 14 SCK
cycles of conversion, are ignored by the LTC1402. The
duty cycle of CONV can be arbitrarily chosen to be used as
a frame sync signal for the processor serial port. A simple
approach to generate CONV is to create a pulse that is one
SCK wide to drive the LTC1402 and then buffer this signal
with the appropriate number of inverters to drive the frame
sync input of the processor serial port. It is good practice
to drive the LTC1402 CONV input first to avoid digital noise
interference during the sample-to-hold transition triggered
by CONV at the start of conversion. Another point to con-
sider is the level of jitter in the CONV signal if the input
signals have fast transients or sinewaves. Some proces-
sors can be programmed to generate a convenient frame
sync pulse at their serial port, but often this signal is de-
rived from a jittery processor phase locked loop clock
multiplier. This is true even if a low jitter crystal clock is the
reference for the processor clock multiplier.
SCK at Pin 15
The rising edge of SCK advances the conversion process
and also udpates each bit in the D
CONV rises, the second rising edge of SCK sends out the
REFREADY bit. Subsequent edges send out the 12 data
bits, with the MSB sent first. A simple approach is to
generate SCK to drive the LTC1402 and then buffer this
signal with the appropriate number of inverters to drive the
serial clock input of the processor serial port. The rising
edge of SCK is guaranteed to coincide with stable data at
D
first to avoid digital noise interference during the internal
bit comparison decision by the internal high speed com-
parator. Unlike the CONV input, the SCK input is not
sensitive to jitter because the input signal is already
sampled and held constant.
D
Upon power-up, the D
the high impedance state. The D
impedance until a new conversion is started. D
out 13 bits in the output data stream after the second rising
edge of SCK after the start of conversion with the rising
OUT
OUT
. It is good practice to drive the LTC1402 SCK input
at Pin 10
OUT
output is automatically reset to
OUT
OUT
output remains in high
data stream. After
OUT
sends