LTC1288CN8 Linear Technology, LTC1288CN8 Datasheet - Page 12

• Manufacturer Part Number: LTC1288CN8
• Description: IC A/D CONV SAMPLING 12BIT 8-DIP
• Manufacturer: Linear Technology

Specifications of LTC1288CN8

• Number Of Bits: 12
• Sampling Rate (per Second): 6.6k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 630µW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADDRESS IN
LTC1285/LTC1288
APPLICATION INFORMATION
Data Transfer
The CLK synchronizes the data transfer with each bit
being transmitted on the falling CLK edge and captured
on the rising CLK edge in both transmitting and receiving
systems.
The LTC1285 does not require a configuration input word
and has no D
shown in the LTC1285 operating sequence. After CS falls
the second CLK pulse enables D
A/D conversion result is output on the D
CS high resets the LTC1285 for the next data exchange.
The LTC1288 first receives input data and then transmits
back the A/D conversion result (half duplex). Because of
the half duplex operation, D
together allowing transmission over just 3 wires: CS, CLK
and DATA (D
Data transfer is initiated by a falling chip select (CS) signal.
After CS falls the LTC1288 looks for a start bit. After the
start bit is received, the 3-bit input word is shifted into the
D
conversion. After one null bit, the result of the conversion
is output on the D
CS should be brought high. This resets the LTC1288 in
preparation for the next data exchange.
Input Data Word
The LTC1285 requires no D
configured to have a single differential input. The conver-
sion result appears on the D
MSB first followed by the LSB sequence. This provides
easy interface to MSB or LSB first serial ports. For MSB
first data the CS signal can be taken high after B0 (see
Figure 1). The LTC1288 clocks data into the D
12
SHIFT MUX
IN
input which configures the LTC1288 and starts the
CS
D
IN
1
IN
1 NULL BIT
IN
/D
pin. A falling CS initiates data transfer as
OUT
OUT
D
U
OUT
).
line. At the end of the data exchange
SHIFT A/D CONVERSION
RESULT OUT
1
U
OUT
IN
IN
OUT
word. It is permanently
and D
line. The data format is
D
W
. After one null bit the
IN
2
OUT
OUT
line. Bringing
D
may be tied
OUT
IN
U
2
input on
LTC1285/88 • AI01
the rising edge of the clock. The input data words are
defined as follows:
Start Bit
The first “logical one” clocked into the D
goes low is the start bit. The start bit initiates the data
transfer. The LTC1288 will ignore all leading zeros which
precede this logical one. After the start bit is received, the
remaining bits of the input word will be clocked in. Further
inputs on the D
cycle.
Multiplexer (MUX) Address
The bits of the input word following the START bit assign
the MUX configuration for the requested conversion. For
a given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of the following tables.
In single-ended mode, all input channels are measured
with respect to GND.
MSB First/LSB First (MSBF)
The output data of the LTC1288 is programmed for
MSB first or LSB first sequence using the MSBF bit.
When the MSBF bit is a logical one, data will appear on
the D
filled in indefinitely following the last data bit. When the
MSBF bit is a logical zero, LSB first data will follow the
normal MSB first data on the D
Sequence).
SINGLE-ENDED
DIFFERENTIAL
MUX MODE
MUX MODE
OUT
line in MSB first format. Logical zeros will be
SGL/DIFF
IN
MUX ADDRESS
LTC1288 Channel Selection
1
1
0
0
START
pin are then ignored until the next CS
ODD/SIGN
SGL/
DIFF
0
1
0
1
ADDRESS
MUX
ODD/
SIGN
0
+
+
–
CHANNEL #
MSB FIRST/
OUT
LSB FIRST
LTC1285/88 • AI02
MSBF
line (see Operating
LTC1285/88 • AI03
1
+
–
+
IN
GND
–
–
input after CS