LTC2411-1CMS#PBF Linear Technology, LTC2411-1CMS#PBF Datasheet - Page 23

• Manufacturer Part Number: LTC2411-1CMS#PBF
• Description: IC A/DCONV DIFF INPUT&REF 10MSOP
• Manufacturer: Linear Technology

Specifications of LTC2411-1CMS#PBF

• Number Of Bits: 24
• Sampling Rate (per Second): 6.8
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
a 13 s (14.2 s) sampling period. Thus, for settling errors
of less than 1ppm, the driving source impedance should
be chosen such that
an external oscillator of frequency f
sampling period is 2/f
than 1ppm,
Input Current
If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 11 shows the
mathematical expressions for the average bias currents
flowing through the IN
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 12. The C
includes the LTC2411/LTC2411-1 pin capacitance (5pF
typical) plus the capacitance of the test fixture used to
obtain the results shown in Figures 13 and 14. A careful
implementation can bring the total input capacitance (C
+ C
than the one predicted by Figures 13 and 14. The effect of
the input dynamic current is almost the same for the
LTC2411 and the LTC2411-1 and measurements of the
LTC2411 with F
For simplicity, two distinct situations can be considered.
For relatively small values of input capacitance (C
0.01 F), the voltage on the sampling capacitor settles
almost completely and relatively large values for the
source impedance result in only small errors. Such values
for C
performance without significant benefits of signal filter-
ing and the user is advised to avoid them. Nevertheless,
when small values of C
parasitics of input multiplexers, wires, connectors or
sensors, the LTC2411/LTC2411-1 can maintain their ex-
ceptional accuracy while operating with relative large
values of source resistance as shown in Figures 13 and
14. These measured results may be slightly different from
the first order approximation suggested earlier because
PAR
IN
) closer to 5pF thus achieving better performance
will deteriorate the converter offset and gain
O
0.14/f
= GND are plotted out as a typical case.
U
EOSC
EOSC
+
13 s/14 = 920ns (1.02 s). When
IN
and IN
U
.
and, for a settling error of less
are unavoidably present as
–
pins as a result of the
W
EOSC
PAR
is used, the
U
capacitor
IN
IN
<
they include the effect of the actual second order input
network together with the nonlinear settling process of
the input amplifiers. For small C
IN
benefit in trying to match the source impedance for the
two pins.
+
and IN
Figure 13. +FS Error vs R
Figure 14. –FS Error vs R
V
V
INCM
INCM
–10
–20
–30
–40
–50
+ 0.5V
– 0.5V
–
Figure 12. An RC Network at IN
50
40
30
20
10
occurs almost independently and there is little
0
0
1
1
IN
IN
V
REF
REF
IN
IN
F
T
V
REF
REF
IN
IN
F
T
O
A
O
A
CC
CC
+
–
+
–
= GND
= 25 C
= GND
LTC2411/LTC2411-1
= 25 C
+
= GND
= 2.5V
+
–
= 5V
= 2.5V
–
= 5V
= 5V
= 5V
= GND
= 5V
= GND
10
10
R
R
C
C
SOURCE
SOURCE
IN
IN
C
C
= 0.001 F
IN
IN
= 0.001 F
C
C
C
C
IN
IN
IN
= 100pF
IN
= 100pF
R
100
R
100
= 0.01 F
SOURCE
= 0.01 F
SOURCE
= 0pF
= 0pF
SOURCE
SOURCE
C
C
IN
IN
( )
( )
1k
1k
IN
at IN
at IN
values, the settling on
C
C
10k
10k
+
+
PAR
PAR
20pF
20pF
or IN
or IN
+
and IN
2411 F14
2411 F13
100k
100k
–
–
IN
LTC2411-1
IN
LTC2411/
(Small C
(Small C
+
–
–
2411 F12
23
IN
IN
)
)