LTC2411-1CMS#PBF Linear Technology, LTC2411-1CMS#PBF Datasheet - Page 19

• Manufacturer Part Number: LTC2411-1CMS#PBF
• Description: IC A/DCONV DIFF INPUT&REF 10MSOP
• Manufacturer: Linear Technology

Specifications of LTC2411-1CMS#PBF

• Number Of Bits: 24
• Sampling Rate (per Second): 6.8
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time t
(if EOC = 0) or t
during the falling edge of EOC). The value of t
(INTERNAL)
SDO
SCK
CS
Hi-Z
SLEEP
> t
EOCtest
EOCtest
BIT 0
EOC
U
after EOC goes LOW (if CS is LOW
CONVERSION
Hi-Z
EOCtest
DATA OUTPUT
TEST EOC
U
after the falling edge of CS
Hi-Z
Figure 9. Internal Serial Clock, Reduced Data Output Length
TEST EOC
W
SLEEP
ANALOG INPUT RANGE
Hi-Z
–0.5V
<t
EOCtest
REF
EOCtest
BIT 31
0.1V TO V
REFERENCE
EOC
TO 0.5V
VOLTAGE
U
1 F
2.7V TO 5.5V
REF
CC
BIT 30
is 23 s
1
2
3
4
5
6
V
REF
REF
IN
IN
GND
CC
LTC2411-1
+
–
LTC2411/
+
–
BIT 29
SIG
SDO
SCK
if the device is using its internal oscillator for the LTC2411
(F
(F
of frequency f
HIGH before time t
state. The conversion result is held in the internal static
shift register.
If CS remains LOW longer than t
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 32nd
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 9. On the rising edge of CS, the device
CS
F
O
O
O
10
9
8
7
DATA OUTPUT
BIT 28
= logic LOW). If F
= logic LOW or HIGH) and 26 s for the LTC2411-1
MSB
3-WIRE
SPI INTERFACE
V
BIT 27
CC
= 50Hz REJECTION (LTC2411)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2411)
= SIMULTANEOUS 50Hz/60Hz REJECTION (LTC2411-1)
EOSC
LTC2411/LTC2411-1
BIT 26
, then t
EOCtest
O
is driven by an external oscillator
EOCtest
, the device remains in the sleep
BIT 8
is 3.6/f
CONVERSION
Hi-Z
EOCtest
TEST EOC
EOSC
, the first rising
2411 F09
V
. If CS is pulled
CC
10k
19