LTC2422CMS#TRPBF Linear Technology, LTC2422CMS#TRPBF Datasheet - Page 17

• Manufacturer Part Number: LTC2422CMS#TRPBF
• Description: IC ADC 2CH 20BIT MICRPWR 10-MSOP
• Manufacturer: Linear Technology

Specifications of LTC2422CMS#TRPBF

• Number Of Bits: 20
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 8. CS
may be permanently tied to ground (Pin 6), simplifying the
user interface or isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after V
applied to SCK at this time determines if SCK is internal or
external. SCK must be driven LOW prior to the end of POR
in order to enter the external serial clock timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can
be continuously monitored at the SDO pin during the
convert and sleep states. EOC may be used as an inter-
rupt to an external controller indicating the conversion
result is ready. EOC = 1 while the conversion is in progress
and EOC = 0 once the conversion enters the low power
sleep state. On the falling edge of EOC, the conversion
result is loaded into an internal static shift register. The
device remains in the sleep state until the first rising edge
of SCK. Data is shifted out the SDO pin on each falling
edge of SCK enabling external circuitry to latch data on
the rising edge of SCK. EOC can be latched on the first
rising edge of SCK. On the 24th falling edge of SCK, SDO
(EXTERNAL)
SDO
SCK
CS
CONVERSION
U
SLEEP
U
CC
exceeds 2.2V. The level
W
BIT 23
EOC
Figure 8. External Serial Clock, CS = 0 Operation
ANALOG INPUT RANGE
(V
CH0/CH1
BIT 22
ZS
REF
REFERENCE VOLTAGE
0V TO FS
ZS
SET
FS
= FS
SET
SET
– 0.12V
U
SET
+ 0.1V TO V
+ 0.12V
SET
– ZS
BIT 21
– 100mV
REF
SIG
SET
1 F
REF
2.7V TO 5.5V
TO
)
CC
BIT 20
EXR
1
2
3
4
5
DATA OUTPUT
V
FS
CH1
ZS
CH0
CC
SET
SET
goes HIGH (EOC = 1) indicating a new conversion has
begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and con-
trol the state of the conversion cycle, see Figure 9.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
LTC2422
BIT 19
MSB
SDO
GND
SCK
CS
F
O
10
9
8
7
6
BIT 18
2-WIRE SERIAL I/O
V
CC
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
LTC2421/LTC2422
BIT 4
BIT 0
LSB
20
CONVERSION
17
24212f
24212 F08