LTC1096IS8 Linear Technology, LTC1096IS8 Datasheet - Page 16

• Manufacturer Part Number: LTC1096IS8
• Description: IC A/D CONV 8BIT SRL IN/OUT8SOIC
• Manufacturer: Linear Technology

Specifications of LTC1096IS8

• Number Of Bits: 8
• Sampling Rate (per Second): 33k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 600µW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
The wake-up time is inherently provided for the LTC1098(L)
with setup time = 1μs (see Figure 2).
Data Transfer
The CLK synchronizes the data transfer with each bit being
transmitted on the falling CLK edge and captured on the
rising CLK edge in both transmitting and receiving sys-
tems. The LTC1098(L) fi rst receives input data and then
transmits back the A/D conversion result (half duplex).
Because of the half duplex operation, D
be tied together allowing transmission over just three
wires: CS, CLK and DATA (D
Data transfer is initiated by a falling chip select (CS) signal.
After CS falls the LTC1098(L) looks for a start bit. After the
start bit is received, the 3-bit input word is shifted into the
D
conversion. After one null bit, the result of the conversion
16
IN
input which confi gures the LTC1098(L) and starts the
D
D
OUT
CLK
CLK
OUT
CS
CS
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.
Hi-Z
HI-Z
t
WAKEUP
t
WAKEUP
t
t
suCS
suCS
IN
/D
OUT
).
NULL
BIT
NULL
BIT
(MSB)
(MSB)
IN
B7
B7
Figure 1. LTC1096(L) Operating Sequence
and D
B6
B6
t
CYC
OUT
t
B5
B5
CONV
t
CONV
may
B4
B4
B3
B3
t
CYC
B2
B2
ADDRESS IN
is output on the D
CS should be brought high. This resets the LTC1098(L) in
preparation for the next data exchange.
The LTC1096(L) does not require a confi guration input
word and has no D
feras shown in the LTC1096(L) operating sequence. After
CS falls, the fi rst CLK pulse enables D
bit, the A/D conversion result is output on the D
Bringing CS high resets the LTC1096(L) for the next data
exchange.
SHIFT MUX
B1
B1
CS
B0
B0
D
IN
B1
POWER
DOWN
1
1 NULL BIT
Hi-Z
B2
OUT
IN
D
B3
OUT
pin. A falling CS initiates data trans-
line. At the end of the data exchange
SHIFT A/D CONVERSION
RESULT OUT
1
B4
B5
B6
D
IN
B7*
2
OUT
POWER
DOWN
. After one null
Hi-Z
D
OUT
10968 F01
2
OUT
10968 AI01
10968fc
line.