MAX19516ETM+ Maxim Integrated Products, MAX19516ETM+ Datasheet - Page 4

• Manufacturer Part Number: MAX19516ETM+
• Description: IC ADC 10BIT 100MSPS DUAL 48TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX19516ETM+

• Number Of Bits: 10
• Sampling Rate (per Second): 100M
• Data Interface: Serial, Parallel
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Conversion Rate: 100 MSPs
• Resolution: 10 bit
• Interface Type: SPI
• Snr: 60.1 dB
• Voltage Reference: 1.25 V
• Supply Voltage (max): 3.5 V
• Supply Voltage (min): 1.7 V
• Maximum Power Dissipation: 3200 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 1.8 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual-Channel, 10-Bit, 100Msps ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
tion = 50Ω, T
4
INTERCHANNEL CHARACTERISTICS
Crosstalk
Gain Match
Offset Match
Phase Match
ANALOG OUTPUTS (CMA, CMB)
CMA, CMB Output Voltage
INTERNAL REFERENCE
REFIO Output Voltage
REFIO Temperature Coefficient
EXTERNAL REFERENCE
REFIO Input-Voltage Range
REFIO Input Resistance
CLOCK INPUTS (CLK+, CLK-)—DIFFERENTIAL MODE
Differential Clock Input Voltage
Differential Input Common-Mode
Voltage
Input Resistance
Input Capacitance
CLOCK INPUTS (CLK+, CLK-)—SINGLE-ENDED MODE (V
Single-Ended Mode Selection
Threshold (V
Allowable Logic Swing (V
Single-Ended Clock Input High
Threshold (V
Single-Ended Clock Input Low
Threshold (V
Input Leakage (CLK+)
Input Leakage (CLK-)
Input Capacitance (CLK+)
AVDD
_______________________________________________________________________________________
= V
PARAMETER
OVDD
A
CLK-
CLK+
CLK+
= -40°C to +85°C, unless otherwise noted. Typical values are at T
= 1.8V, internal reference, differential clock, V
)
)
)
CLK+
)
SYMBOL
V
V
R
TC
V
REFOUT
C
R
REFIN
REFIN
COM
CLK
CLK
REF
f
f
f
f
f
Default programmable setting
Self-biased
DC-coupled clock signal
Differential, default
Differential, internal termination selected
Common mode
To ground, each input
V
V
V
INA
INA
IN
IN
IN
CLK+
CLK+
CLK-
= 70MHz
= 70MHz
= 70MHz
or f
or f
= 0V
= V
= 0V
INB
INB
AVDD
= 70MHz at -1dBFS
= 175MHz at -1dBFS
CLK-
CLK
CONDITIONS
= 1.8V or 3.3V
< 0.1V)
= 1.5V
P-P
, f
CLK
A
= +25°C.) (Note 1)
= 100MHz, A
0.85
1.23
-150
IN
MIN
-0.5
1.5
= -0.5dBFS, data output termina-
0 - V
0.4 to 2.0
1.0 to 1.4
1.25 +5/
< ±60
±20%
±0.05
-10%
±0.1
±0.5
TYP
1.25
100
0.9
1.2
95
85
10
10
9
3
3
AVDD
MAX
+0.5
0.95
1.27
-50
0.1
0.3
D eg r ees
ppm/°C
UNITS
%FSR
V
dBc
dB
kΩ
kΩ
kΩ
pF
µA
µA
pF
P-P
Ω
V
V
V
V
V
V
V
V