MAX1277AETC+ Maxim Integrated Products, MAX1277AETC+ Datasheet - Page 9

• Manufacturer Part Number: MAX1277AETC+
• Description: IC ADC 12BIT 1.5MSPS 12-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX1277AETC+

• Number Of Bits: 12
• Sampling Rate (per Second): 1.5M
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1.35W
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 12-WQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 3. Functional Diagram
The MAX1277/MAX1279 use an input T/H and succes-
sive-approximation register (SAR) circuitry to convert
an analog input signal to a digital 12-bit output. The
serial interface requires only three digital lines (SCLK,
CNVST, and DOUT) and provides easy interfacing to
microprocessors (µPs) and DSPs. Figure 3 shows the
simplified internal structure for the MAX1277/MAX1279.
RGND
REF
AIN +
AIN -
Differential, 12-Bit ADCs with Internal Reference
5, 11
PIN
10
12
—
1
2
3
4
6
7
8
9
TRACK AND
HOLD
MAX1279
MAX1277
CNVST
NAME
RGND
DOUT
SCLK
AIN+
GND
AIN-
N.C.
2.048V
REF
V
_______________________________________________________________________________________
V
EP
REF
DD
1.5Msps, Single-Supply, Low-Power, True-
L
Detailed Description
12-BIT
SAR
ADC
V
Negative Analog Input
Reference Voltage Output. Internal 2.048V reference output. Bypass REF with a 0.01µF capacitor and
a 4.7µF capacitor to RGND.
Reference Ground. Connect RGND to GND.
Positive Analog Supply Voltage (+2.7V to +3.6V). Bypass V
capacitor to GND.
No Connection
Ground. GND is internally connected to EP.
Positive Logic Supply Voltage (1.8V to V
to GND.
Serial Data Output. Data is clocked out on the rising edge of SCLK.
Convert Start. Forcing CNVST high prepares the part for a conversion. Conversion begins on the
falling edge of CNVST. The sampling instant is defined by the falling edge of CNVST.
Serial Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed.
Positive Analog Input
Exposed Paddle. EP is internally connected to GND.
DD
LOGIC AND
CONTROL
TIMING
OUTPUT
BUFFER
GND
V
L
DOUT
CNVST
SCLK
Figure 4. Equivalent Input Circuit
DD
). Bypass V
AIN+
AIN+
AIN-
AIN-
FUNCTION
L
with a 0.01µF capacitor and a 10µF capacitor
C
C
C
C
IN+
IN-
IN+
IN-
DD
R
R
R
R
IN+
IN-
IN+
IN-
with a 0.01µF capacitor and a 10µF
HOLD/CONVERSION MODE
ACQUISITION MODE
V
V
AZ
AZ
Pin Description
COMP
COMP
CAPACITIVE
CAPACITIVE
CONTROL
CONTROL
LOGIC
LOGIC
DAC
DAC
9