AD9269BCPZ-65 Analog Devices Inc, AD9269BCPZ-65 Datasheet - Page 33

• Manufacturer Part Number: AD9269BCPZ-65
• Description: IC ADC 16BIT SER 2CH 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9269BCPZ-65

• Data Interface: Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 65M
• Number Of Converters: 2
• Power Dissipation (max): 199.8mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Resolution (bits): 16bit
• Sampling Rate: 65MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Addr.
(Hex)
0x0D
0x0E
0x10
0x14
0x15
0x16
0x17
0x19
0x1A
0x1B
0x1C
0x24
Register
Name
Test mode (local)
BIST enable
Offset adjust
(local)
Output mode
OUTPUT_ADJUST
OUTPUT_PHASE
OUTPUT_DELAY
USER_PATT1_LSB
USER_PATT1_MSB
USER_PATT2_LSB
USER_PATT2_MSB
MISR_LSB
(MSB)
Bit 7
User test mode
(local)
00 = single
01 = alternate
10 = single once
11 = alternate
once
Open
8-bit device offset adjustment [7:0] (local)
Offset adjust in LSBs from +127 to −128 (twos complement format)
00 = 3.3 V CMOS
10 = 1.8 V CMOS
3.3 V DCO
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
DCO
output
polarity
0 =
normal
1 =
inverted
(local)
Enable
DCO
delay
B7
B15
B7
B15
Open
Bit 6
Open
Open
Open
B6
B14
B6
B14
Open
Bit 5
Reset PN
long gen
Open
Output mux
enable
(interleaved)
Open
Enable
data
delay
B5
B13
B5
B13
Open
1.8 V DCO drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes (default)
11 = 4 stripes
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Bit 4
Reset PN
short
gen
Open
Output
disable
(OEB)
(local)
Open
Open
B4
B4
Open
B12
B12
Open
B3
B3
Open
B11
B11
Bit 3
Open
Open
3.3 V data
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
Open
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = one/zero word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
Output test mode [3:0] (local)
Bit 2
BIST init
Output
invert
(local)
Input clock phase adjust, Bits[2:0]
(Value is number of input clock
cycles of phase delay)
B2
B10
B2
B10
Open
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
DCO/data delay, Bits[2:0]
000 = 0.56 ns
001 = 1.12 ns
010 = 1.68 ns
011 = 2.24 ns
100 = 2.80 ns
101 = 3.36 ns
110 = 3.92 ns
111 = 4.48 ns
Bit 1
Open
00 = offset binary
01 = twos
complement
10 = gray code
11 = offset binary
(local)
1.8 V data
drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes
(default)
11 = 4 stripes
B1
B9
B1
B9
Open
(LSB)
Bit 0
B0
B8
B0
B8
B0
BIST
enable
Default
Value
(Hex)
0x00
0x00
0x00
0x00
0x22
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Least significant
Comments
When set, the test
data is placed on
the output pins
in place of
normal data
When Bit 0 is set,
the BIST function
is initiated
Device offset trim
Configures the
outputs and the
format of the data
Determines
CMOS output
drive strength
properties
On devices that
utilize global
clock divide,
determines
which phase of
the divider
output is used to
supply the
output clock;
internal latching
is unaffected
This sets the fine
output delay of
the output clock
but does not
change internal
timing
User-Defined
Pattern 1, LSB
User-defined
Pattern 1, MSB
User-Defined
Pattern 2, LSB
User-Defined
Pattern 2, MSB
byte of MISR;
read only
AD9269