AD9265BCPZ-80 Analog Devices Inc, AD9265BCPZ-80 Datasheet - Page 38

• Manufacturer Part Number: AD9265BCPZ-80
• Description: IC ADC 16BIT 80MSPS 48LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9265BCPZ-80

• Data Interface: Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 80M
• Number Of Converters: 1
• Power Dissipation (max): 258mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Resolution (bits): 16bit
• Sampling Rate: 80MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Supply Voltage Range - Digital: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9265
Addr.
(Hex)
0x14
0x16
0x17
0x18
0x24
0x25
0x30
Digital Feature Control Register
0x100
Register
Name
Output
mode
Clock phase
control
DCO output
delay
VREF select
BIST
signature LSB
BIST
signature
MSB
Dither
enable
Sync control
Bit 7 (MSB)
Drive
strength
0 = ANSI LVDS
1 = reduced
LVDS
Invert DCO
clock
Open
Open
Reference voltage selection
11 = 2.0 V p-p (default)
Open
00 = 1.25 V p-p
10 = 1.75 V p-p
01 = 1.5 V p-p
Bit 6
Output
type
0 = CMOS
1 = LVDS
Open
Open
Open
Open
Bit 5
Open
Open
Open
Open
Open
Open
BIST Signature[15:8]
BIST Signature[7:0]
Rev. A | Page 38 of 44
Bit 4
Output
enable
bar
Open
Open
Open
enable
Dither
(delay = 2500 ps × register value/31)
Bit 3
Open
Open
Open
Open
Open
DCO clock delay
11110 = 2419 ps
11111 = 2500 ps
00010 = 161 ps
00001 = 81 ps
00000 = 0 ps
Bit 2
Output
invert
Open
Open
Clock
divider
next sync
only
Input clock divider phase adjust
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
001 = 1 input clock cycle
…
000 = no delay
Bit 1
Open
Open
Clock
divider
sync
enable
00 = offset binary
11 = offset binary
01 = gray code
complement
01 = twos
Output
format
Bit 0 (LSB)
Open
Open
Master
sync
enable
Default
Value
(Hex)
0x00
0x00
0x00
0xC0
0x00
0x00
0x00
0x00
Default Notes/
Comments
Configures the
outputs and
the format of
the data
Allows
selection of
clock delays
into the input
clock divider
Read only
Read only