MAX1186ECM+D Maxim Integrated Products, MAX1186ECM+D Datasheet - Page 14

• Manufacturer Part Number: MAX1186ECM+D
• Description: IC ADC 10BIT 40MSPS DL 48-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1186ECM+D

• Number Of Bits: 10
• Sampling Rate (per Second): 40M
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 150mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Conversion Rate: 40 MSPs
• Resolution: 10 bit
• Snr: 59.5 dB
• Voltage Reference: 2.048 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Power Dissipation: 2430 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 3 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 5 depicts a typical application circuit containing
two single-ended to differential converters. The internal
reference provides a V
shifting purposes. The input is buffered and then split to
a voltage follower and inverter. One lowpass filter per
ADC suppresses some of the wideband noise associat-
ed with high-speed operational amplifiers that follows
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Figure 3. Timing Diagram for Multiplexed Outputs
Figure 4. Output Timing Diagram
14
D0A/B–D9A/B
OUTPUT
CHB
D0A/B–D9A/B
______________________________________________________________________________________
CLK
CHA
t
t
A/B
DA/B
DOB
OE
IMPEDANCE
HIGH
t
CL
CHB
D0B
Applications Information
t
CLK
t
ENABLE
t
CH
CHA
D1A
DD
/ 2 output voltage for level
t
DOA
CHB
D1B
VALID DATA
t
DISABLE
5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB)
CHA
D2A
CHB
D2B
IMPEDANCE
HIGH
CHA
D3A
the amplifiers. The user may select the R
values to optimize the filter performance, to suit a par-
ticular application. For the application in Figure 5, a
R
vent ringing and oscillation. The 22pF C
acts as a small bypassing capacitor.
An RF transformer (Figure 6) provides an excellent
solution to convert a single-ended source signal to a
fully differential signal, required by the MAX1186 for
optimum performance. Connecting the center tap of the
transformer to COM provides a V
the input. Although a 1:1 transformer is shown, a step-
up transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the over-
all distortion.
In general, the MAX1186 provides better SFDR and
THD with fully differential input signals than single-
ended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower as both inputs (INA+, INA- and/or INB+, INB-) are
balanced, and each of the ADC inputs only requires
half the signal swing compared to single-ended mode.
CHB
D3B
ISO
of 50Ω is placed before the capacitive load to pre-
CHA
D4A
CHB
D4B
Using Transformer Coupling
CHA
D5A
CHB
D5B
DD
/ 2 DC level shift to
CHA
D6A
IN
ISO
capacitor
CHB
D6B
and C
IN