MAX1238EEE+ Maxim Integrated Products, MAX1238EEE+ Datasheet - Page 16

• Manufacturer Part Number: MAX1238EEE+
• Description: IC ADC 12-BIT 94KSPS 16-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1238EEE+

• Number Of Bits: 12
• Sampling Rate (per Second): 94.4k
• Data Interface: I²C, Serial
• Number Of Converters: 1
• Power Dissipation (max): 666.7mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Number Of Adc Inputs: 12
• Architecture: SAR
• Conversion Rate: 94.4 KSPs
• Resolution: 12 bit
• Interface Type: I2C
• Voltage Reference: Internal 4.096 V
• Supply Voltage (max): 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(FIFO) sequence. If AIN_/REF is set to be a reference
input or output (SEL1 = 1, Table 6), AIN_/REF is exclud-
ed from a multichannel scan. The memory contents can
be read continuously. If reading continues past the
result stored in memory, the pointer wraps around and
point to the first result. Note that only the current con-
version results is read from memory. The device must
be addressed with a read command to obtain new con-
version results.
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
Figure 10. Internal Clock Mode Read Cycles
Figure 11. External Clock Mode Read Cycle
16
A. SINGLE CONVERSION WITH INTERNAL CLOCK
B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
1
S
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
A. SINGLE CONVERSION WITH EXTERNAL CLOCK
1
S
1
S
1
S
______________________________________________________________________________________
SLAVE ADDRESS
SLAVE ADDRESS
SLAVE ADDRESS
SLAVE ADDRESS
MASTER TO SLAVE
SLAVE TO MASTER
MASTER TO SLAVE
SLAVE TO MASTER
7
t
ACQ
7
7
7
t
ACQ1
1 1
R
A
1 1
R
1 1
R
1 1
R
A
CLOCK STRETCH
A
A
t
t
t
ACQ
ACQ1
CONV
RESULT 1 (4 MSBs)
t
CONV1
RESULT (4 MSBs)
CLOCK STRETCH
8
8
RESULT 4 MSBs
t
ACQ2
t
CONV2
8
1
A
1
A
t
CONV
t
CONV1
RESULT 2 (8 LSBs)
RESULT (8 LSBs)
A
CLOCK STRETCH
8
8
RESULT 8 LSBs
t
t
ACQN
CONVN
8
1
A
1
A
t
ACQ2
RESULT 1 ( 4MSBs)
1
A
P OR Sr
P or Sr
1
8
1
The internal clock mode’s clock stretching quiets the
SCL bus signal reducing the system noise during con-
version. Using the internal clock also frees the bus
master (typically a microcontroller) from the burden of
running the conversion clock, allowing it to perform
other tasks that do not need to use the bus.
When configured for external clock mode (CLK = 1),
the MAX1236–MAX1239 use the SCL as the conversion
t
RESULT N (4 MSBs)
1
A
ACQN
NUMBER OF BITS
NUMBER OF BITS
RESULT 1 (8 LSBs) A
8
8
1
1
A
t
CONVN
RESULT N (4MSBs)
RESULT N (8 LSBs)
8
8
1
A
RESULT N (8LSBs)
A
1
8
P OR Sr
1
1
A
External Clock
P or Sr
1
NUMBER OF BITS
NUMBER OF BITS