MAX1238EEE+ Maxim Integrated Products, MAX1238EEE+ Datasheet - Page 11

• Manufacturer Part Number: MAX1238EEE+
• Description: IC ADC 12-BIT 94KSPS 16-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1238EEE+

• Number Of Bits: 12
• Sampling Rate (per Second): 94.4k
• Data Interface: I²C, Serial
• Number Of Converters: 1
• Power Dissipation (max): 666.7mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Number Of Adc Inputs: 12
• Architecture: SAR
• Conversion Rate: 94.4 KSPs
• Resolution: 12 bit
• Interface Type: I2C
• Voltage Reference: Internal 4.096 V
• Supply Voltage (max): 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

swing from (V
ing damage to the device. For accurate conversions,
the inputs must not go more than 50mV below GND or
above V
The SGL/DIF of the configuration byte configures the
MAX1236–MAX1239 analog-input circuitry for single-
ended or differential inputs (Table 2). In single-ended
mode (SGL/DIF = 1), the digital conversion results are the
difference between the analog input selected by CS[3:0]
and GND (Table 3). In differential mode (SGL/ DIF = 0),
the digital conversion results are the difference between
the “+” and the “-” analog inputs selected by CS[3:0]
(Table 4).
When operating in differential mode, the BIP/UNI bit of
the set-up byte (Table 1) selects unipolar or bipolar
operation. Unipolar mode sets the differential input
range from 0 to V
input in unipolar mode causes the digital output code
to be zero. Selecting bipolar mode sets the differential
input range to ±V
ry in unipolar mode and two’s complement in bipolar
mode, see the Transfer Functions section.
In single-ended mode, the MAX1236–MAX1239 al-
ways operates in unipolar mode irrespective of
BIP/UNI. The analog inputs are internally referenced to
GND with a full-scale input range from 0V to V
The MAX1236–MAX1239 feature a 2-wire interface con-
sisting of a serial data line (SDA) and serial clock line
(SCL). SDA and SCL facilitate bidirectional communica-
tion between the MAX1236–MAX1239 and the master at
rates up to 1.7MHz. The MAX1236–MAX1239 are slaves
that transfer and receive data. The master (typically a
microcontroller) initiates data transfer on the bus and
generates the SCL signal to permit that transfer.
SDA and SCL must be pulled high. This is typically done
with pullup resistors (750Ω or greater) (see the Typical
Operating Circuit ). Series resistors (R
protect the input architecture of the MAX1236–MAX1239
from high voltage spikes on the bus lines and minimize
crosstalk and undershoot of the bus signals.
One data bit is transferred during each SCL clock
cycle. A minimum of 18 clock cycles are required to
transfer the data in or out of the MAX1236–MAX1239.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
DD
.
GND
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
Single-Ended/Differential Input
SCL is stable are considered control
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
REF
______________________________________________________________________________________
- 0.3V) to (V
REF
/2. The digital output code is bina-
. A negative differential analog
2-Wire Digital Interface
DD
+ 0.3V) without caus-
Unipolar/Bipolar
S
) are optional. They
Bit Transfer
REF
.
signals (see the START and STOP Conditions section).
Both SDA and SCL remain high when the bus is not
busy.
The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA while SCL is high.
The master terminates a transmission with a STOP condi-
tion (P), a low-to-high transition on SDA while SCL is high
(Figure 5). A repeated START condition (Sr) can be used
in place of a STOP condition to leave the bus active and
the interface mode unchanged (see HS mode).
Data transfers are acknowledged with an acknowledge
bit (A) or a not-acknowledge bit (A). Both the master
and the MAX1236–MAX1239 (slave) generate acknowl-
edge bits. To generate an acknowledge, the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse
(Figure 6). To generate a not-acknowledge, the receiv-
er allows SDA to be pulled high before the rising edge
of the acknowledge-related clock pulse and leaves
SDA high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master should reattempt
communication at a later time.
Figure 5. START and STOP Conditions
Figure 6. Acknowledge Bits
SDA
SCL
SDA
SCL
S
S
1
START and STOP Conditions
2
Sr
NOT ACKNOWLEDGE
Acknowledge Bits
ACKNOWLEDGE
8
P
9
11