KAD5514P-25Q48 Intersil, KAD5514P-25Q48 Datasheet
KAD5514P-25Q48
Specifications of KAD5514P-25Q48
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KAD5514P-25Q48 Summary of contents
Page 1
... Digital output data is presented in selectable LVDS or CMOS formats. The KAD5514P is available in 72- and 48-contact QFN packages with an exposed paddle. Operating from a 1.8V supply, performance is specified over the full industrial temperature range (-40°C to +85°C). ...
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... PART NUMBER KAD5514P-25Q72 (Note 1) KAD5514P-25 Q72EP-I KAD5514P-21Q72 (Note 1) KAD5514P-21 Q72EP-I KAD5514P-17Q72 (Note 1) KAD5514P-17 Q72EP-I KAD5514P-12Q72 (Note 1) KAD5512P-17 Q72EP-I KAD5514P-25Q48 (Note 2) KAD5512P-25 Q48EP-I KAD5514P-21Q48 (Note 2) KAD5514P-21 Q48EP-I KAD5514P-17Q48 (Note 2) KAD5514P-17 Q48EP-I KAD5514P-12Q48 (Note 2) KAD5514P-12 Q48EP-I NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
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... Analog Input .................................................................. 19 Clock Input..................................................................... 19 Jitter ............................................................................... 20 Voltage Reference ......................................................... 20 Digital Outputs ............................................................... 20 Over-Range Indicator .................................................... 20 Power Dissipation .......................................................... 20 Nap/Sleep ...................................................................... 21 Data Format................................................................... 21 3 KAD5514P Serial Peripheral Interface ............................................. 22 SPI Physical Interface ................................................... 23 SPI Configuration .......................................................... 24 Device Information ........................................................ 24 Indexed Device Configuration/Control .......................... 24 Global Device Configuration/Control............................. 25 Device Test ................................................................... 26 SPI Memory Map .......................................................... 27 Equivalent Circuits ......................................................... 29 72 Pin/48 Pin Package Options ...
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... P-P = -1dBFS Maximum Conversion Rate IN SAMPLE KAD5514P-17 KAD5514P-12 (Note 7) (Note 7) MAX MIN TYP MAX MIN TYP 1.54 1.4 1.47 1.54 1.4 1.47 500 500 2.6 2 -10 ±2 10 -10 ±2 ± ...
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... Maximum Conversion Rate SAMPLE KAD5514P-17 KAD5514P-12 (Note 7) (Note 7) TYP MAX MIN TYP MAX 378 406 345 376 339 309 136 151 129 143 ...
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... Mode 950 -500µA OVDD - 0 1mA -1dBFS Maximum Conversion Rate IN SAMPLE KAD5514P-17 KAD5514P-12 (Note 7) (Note 7) MAX MIN TYP MAX MIN TYP -94.5 -94.9 -91.7 -85.7 -12 - 950 950 specifications apply for 10pF load on each digital output. OVDD TYP MAX -12 -5 .63 25 ...
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... PD ODD BITS EVEN BITS ODD BITS EVEN BITS D[12/10/8/6/4/2/0] N-L N FIGURE 2A. DDR FIGURE 2. CMOS TIMING DIAGRAM (See “Digital Outputs” on page 20) 7 KAD5514P CLKN CLKP CLKOUTN CLKOUTP D[13/0]P ODD BITS EVEN BITS EVEN BITS N N D[13/0]N INP INN ...
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... SPI Interface timing is directly proportional to the ADC sample period (4ns at 250Msps). 11. The SPI may operate asynchronously with respect to the ADC sample clock. 12. The CSB setup time increases in sleep mode due to the reduced power state, CSB setup time in Nap mode is equal to normal mode CSB setup time (4ns min). 8 KAD5514P CONDITION SYMBOL t A ...
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... D6P [D6] 43 D7N [NC] 44 D7P [D7] 9 KAD5514P LVDS [LVCMOS] FUNCTION SDR MODE 1.8V Analog Supply Do Not Connect Analog Ground Analog Input Negative, Positive Common Mode Output Tri-Level Clock Divider Control Clock Input True, Complement Tri-Level Output Mode (LVDS, LVCMOS) Tri-Level Power Control (Nap, Sleep modes) ...
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... SCLK 69 SDIO 70 OUTFMT Exposed Paddle AVSS NOTE: LVCMOS Output Mode Functionality is shown in brackets ( Connection) 10 KAD5514P LVDS [LVCMOS] FUNCTION SDR MODE LVDS Bias Resistor LVDS Clock Output Complement [NC in LVCMOS] LVDS Clock Output True [ LVCMOS CLKOUT] LVDS Bit 8 Output Complement [NC in LVCMOS] ...
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... Pinout 72 71 AVDD 1 DNC 2 DNC 3 4 DNC 5 DNC 6 AVDD 7 AVSS 8 AVSS 9 VINN 10 VINP 11 AVSS 12 AVDD 13 DNC 14 DNC 15 VCM 16 CLKDIV 17 DNC DNC KAD5514P KAD5514 (72 LD QFN) TOP VIEW Connect Thermal Pad to AVSS FIGURE 3. PIN CONFIGURATION D10P 53 D10N 52 D9P 51 D9N 50 D8P 49 D8N 48 CLKOUTP ...
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... KAD5514P LVDS [LVCMOS] NAME AVDD 1.8V Analog Supply DNC Do Not Connect AVSS Analog Ground VINN, VINP Analog Input Negative, Positive VCM Common Mode Output CLKP, CLKN Clock Input True, Complement NAPSLP Tri-Level Power Control (Nap, Sleep Modes) RESETN Power-on Reset (Active Low, see “User-Initiated Reset” on page 18) ...
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... LVDS Over Range True [OR] [LVCMOS Over Range] SDO SPI Serial Data Output (4.7kΩ pull-up to OVDD is required) CSB SPI Chip Select (active low) SCLK SPI Clock SDIO SPI Serial Data Input/Output AVSS Analog Ground KAD5514P (48 LD QFN) TOP VIEW Connect Thermal Pad to AVSS ...
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... SFDR SNR 100 130 160 SAMPLE RATE (MSPS) FIGURE 9. SNR AND SFDR KAD5514P All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V +25° Conversion Rate (per speed grade). -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 ...
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... CODE FIGURE 15. NOISE HISTOGRAM 15 KAD5514P All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V +25° Conversion Rate (per speed grade). (Continued) 0.5 ...
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... IMD = -89.2dBFS -20 -40 -60 -80 -100 -120 0M 20M 40M 60M FREQUENCY (Hz) FIGURE 21. TWO-TONE SPECTRUM @ 70MHz 16 KAD5514P All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V +25° Conversion Rate (per speed grade). (Continued) 0 -20 -40 -60 -80 -100 -120 0M ...
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... Theory of Operation Functional Description The KAD5514P is based upon a 12-bit, 250MSPS A/D converter core that utilizes a pipelined successive approximation architecture (Figure 23). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge-domain techniques are used to successively compare the input to a series of reference charges ...
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... OVDD the case during power-on reset, the SDO, RESETN and DNC pins must be in the proper state for the calibration to successfully execute. The performance of the KAD5514P changes with variations in temperature, supply voltage or sample rate. The extent of these changes may necessitate recalibration, depending on system performance requirements ...
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... VCM. The value of the shunt resistor should be determined based on the desired load impedance. The differential input resistance of the KAD5514P is 500Ω. The SHA design uses a switched capacitor input stage (see Figure 43), which creates current spikes when the sampling capacitance is reconnected to the input voltage ...
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... The output code does not wrap around during an over-range condition. The OR bit is updated at the sample rate. Power Dissipation The power dissipated by the KAD5514P is primarily dependent on the sample rate and the output modes: LVDS vs CMOS and DDR vs SDR. There is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate ...
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... NAPSLP PIN AVSS Float AVDD 21 KAD5514P The power-down mode can also be controlled through the SPI port, which overrides the NAPSLP pin setting. Details on this are contained in the “Serial Peripheral Interface” on page 22. This is an indexed function when controlled from the SPI, but a global function when driven from the pin. ...
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... Mapping of the input voltage to the various data formats is shown in Table 5. CSB SCLK SDIO R CSB SCLK SDIO KAD5514P TABLE 5. INPUT VOLTAGE TO OUTPUT CODE MAPPING • • • • INPUT VOLTAGE OFFSET BINARY –Full Scale –Full Scale + 1LSB • • • • Mid–Scale +Full Scale – 1LSB +Full Scale Serial Peripheral Interface • ...
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... The SPI port operates in a half duplex master/slave configuration, with the KAD5514P functioning as a slave. Multiple slave devices can interface to a single master in three-wire mode only, since the SDO output of an unaddressed device is asserted in four-wire mode ...
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... CSB pin is not available. In that case, setting the burst_end address determines the end of the transfer. During a write operation, the user must be cautious to transmit the correct number of bytes based on the starting and ending addresses. 24 KAD5514P CSB STALLING DATA WORD 1 FIGURE 39. 2-BYTE TRANSFER LAST LEGAL CSB STALLING DATA WORD 1 FIGURE 40 ...
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... SLIP TWICE FIGURE 41. PHASE SLIP: CLK ÷ 4 MODE, f ADDRESS 0X72: CLOCK_DIVIDE 0x24[7:0] The KAD5514P has a selectable clock divider that can be FINE GAIN set to divide by four, two or one (no division). By default, the 256 tri-level CLKDIV pin selects the divisor (refer to “Clock Input” ...
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... ADDRESS 0X73: OUTPUT_MODE_A The output_mode_A register controls the physical output format of the data, as well as the logical coding. The KAD5514P can present output data in two physical formats: LVDS or LVCMOS. Additionally, the drive strength in LVDS mode can be set high (3mA) or low (2mA). By default, the tri-level OUTMODE pin selects the mode and drive level (refer to “ ...
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... KAD5514P ADDRESS 0XC2: USER_PATT1_LSB ADDRESS 0XC3: USER_PATT1_MSB These registers define the lower and upper eight bits, WORD 2 respectively, of the first user-defined test word. ADDRESS 0XC2: USER_PATT2_LSB 0x8000 N/A ADDRESS 0XC3: USER_PATT2_MSB N/A These registers define the lower and upper eight bits, ...
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... B15 C6-FF reserved NOTE: 13. At power-up, the DDR Enable bit logic ‘0’ for the 72 pin package and set to a logic ‘1’ internally for the 48 pin package by an internal pull-up.. 28 KAD5514P TABLE 16. SPI MEMORY MAP (Continued) Bit 6 Bit 5 Bit 4 Bit 3 ...
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... AVDD Ω 75kO 280O Ω INPUT Ω 75kO FIGURE 45. TRI-LEVEL DIGITAL INPUTS OVDD 2mA OR 3mA DATA DATA OVDD DATA DATA 2mA OR 3mA FIGURE 47. LVDS OUTPUTS 29 KAD5514P CLKP TO CHARGE PIPELINE Φ CHARGE PIPELINE Φ CLKN AVDD (20k PULL-UP ON RESETN TO SENSE LOGIC INPUT Ω ...
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... PC board layout. Many complex board designs benefit from isolating the analog and digital sections. Analog supply and ground planes should be laid out under signal and clock inputs. Locate the digital planes 30 KAD5514P + – FIGURE 49. VCM_OUT OUTPUT under outputs and logic pins. Grounds should be joined under the chip ...
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... ADC’s transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. 31 KAD5514P Least Significant Bit (LSB) is the bit that has the smallest value or weight in a digital word. Its value in terms of input N ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 32 KAD5514P CHANGE FN6804.2 September 10, 2009 ...
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... Package Outline Drawing L48.7x7E 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 2/09 7.00 PIN 1 INDEX AREA 6 (4X) 0.15 TOP VIEW 6.80 Sq 5.60 Sq TYPICAL RECOMMENDED LAND PATTERN 33 KAD5514P Exp. DAP 7.00 5.60 Sq. 25 0.90 Max 44X 0.50 C 48X 0.25 48X 0.60 NOTES: 1 ...
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... Package Outline Drawing L72.10x10D 72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 11/08 10.00 PIN 1 INDEX AREA 6 (4X) 0.15 TOP VIEW 9.80 Sq 6.00 Sq TYPICAL RECOMMENDED LAND PATTERN 34 KAD5514P 10. 72X 0.40 BOTTOM VIEW 0.90 Max 68X 0.50 72X 0. REF C 72X 0.60 NOTES: 1. Dimensions are in millimeters. ...