CS5381-KSZ Cirrus Logic Inc, CS5381-KSZ Datasheet - Page 15

• Manufacturer Part Number: CS5381-KSZ
• Description: IC ADC AUD 120DB 192KHZ 24-SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5381-KSZ

• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Number Of Converters: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 216k
• Data Interface: Serial
• Power Dissipation (max): 445mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 192 KSPS
• Resolution: 24 bit
• Number Of Adc Inputs: 2
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Power Consumption: 260 mW
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1592 - REFERENCE DESIGN CS5381 AUD ADC598-1008 - BOARD EVAL FOR CS5381 192KHZ ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1091-5

DS563F2
3. APPLICATIONS
3.1
3.2
3.2.1
M1 (Pin 14)
Operational Mode/Sample Rate Range Select
The output sample rate, Fs, can be adjusted from 2 kHz to 216 kHz. The CS5381 must be set to the proper
speed mode via the mode pins, M1 and M0. Refer to
System Clocking
The device supports operation in either Master Mode, where the left/right and serial clocks are synchronous-
ly generated on-chip, or Slave Mode, which requires external generation of the left/right and serial clocks.
The device also includes a master clock divider in Master Mode where the master clock will be internally
divided prior to any other internal circuitry when MDIV is enabled, set to logic 1. In Slave Mode, the MDIV
pin needs to be disabled, set to logic 0.
Master Mode
In Master mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived
from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown
in
MCLK
0
0
1
1
Figure
23. Refer to
M0 (Pin 13)
0
1
0
1
÷ 1
÷ 2
Table 2
Figure 23. CS5381 Master Mode Clocking
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Reserved
for common master clock frequencies.
MDIV
1
0
Table 1. CS5381 Mode Control
MODE
Table
÷ 256
÷ 128
÷ 64
÷ 4
÷ 2
÷ 1
1.
Double
Double
Speed
Speed
Speed
Single
Speed
Speed
Speed
Single
Quad
Quad
2 kHz - 54 kHz
50 kHz - 108 kHz
100 kHz - 216 kHz
Output Sample Rate (Fs)
M1
00
01
10
00
01
10
M0
LRCK Output
(Equal to Fs)
SCLK Output
CS5381
15