CS5381-KSZ Cirrus Logic Inc, CS5381-KSZ Datasheet - Page 10

IC ADC AUD 120DB 192KHZ 24-SOIC

CS5381-KSZ

Manufacturer Part Number
CS5381-KSZ
Description
IC ADC AUD 120DB 192KHZ 24-SOIC
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS5381-KSZ

Package / Case
24-SOIC (0.300", 7.50mm Width)
Number Of Converters
2
Number Of Bits
24
Sampling Rate (per Second)
216k
Data Interface
Serial
Power Dissipation (max)
445mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Conversion Rate
192 KSPS
Resolution
24 bit
Number Of Adc Inputs
2
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 10 C
Mounting Style
SMD/SMT
Power Consumption
260 mW
Supply Voltage (max)
5.25 V
Supply Voltage (min)
4.75 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1592 - REFERENCE DESIGN CS5381 AUD ADC598-1008 - BOARD EVAL FOR CS5381 192KHZ ADC
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1091-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS5381-KSZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
CS5381-KSZR
Manufacturer:
RENESAS
Quantity:
21 000
Part Number:
CS5381-KSZR
0
10
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
(Logic “0” = GND = 0 V; Logic “1” = VL, C
Output Sample Rate
OVFL to LRCK Edge Setup Time
OVFL to LRCK Edge Hold Time
OVFL time-out on overrange condition
MCLK Specifications
MCLK Period
MCLK Duty Cycle
Master Mode
SCLK falling to LRCK transition
SCLK falling to SDOUT valid
SCLK Duty Cycle
Slave Mode
Output Sample Rate
LRCK Duty Cycle
SCLK Period
SCLK Duty Cycle
SDOUT valid before SCLK rising
SDOUT valid after SCLK rising
SCLK falling to LRCK transition
Output Sample Rate
LRCK Duty Cycle
SCLK Period
SCLK Duty Cycle
SDOUT valid before SCLK rising
SDOUT valid after SCLK rising
SCLK falling to LRCK transition
Output Sample Rate
LRCK Duty Cycle
SCLK Period
SCLK Duty Cycle
SDOUT valid before SCLK rising
SDOUT valid after SCLK rising
SCLK falling to LRCK transition
Single-Speed
Double-Speed
Quad-Speed
Parameter
Fs = 44.1, 88.2, 176.4 kHz
Fs = 48, 96, 192 kHz
Double-Speed Mode
Single-Speed Mode
Quad-Speed Mode
L
= 20 pF)
Symbol
t
t
t
t
t
t
t
setup
sclkw
sclkw
sclkw
t
t
t
t
t
t
t
t
t
t
hold
clkw
mslr
Fs
Fs
Fs
Fs
Fs
Fs
sdo
slrd
slrd
slrd
stp
hld
stp
hld
stp
hld
16/f
1/f
Min
100
145
145
100
-20
-20
-20
50
36
40
40
45
10
50
40
45
10
40
72
45
10
-8
2
2
5
5
5
sclk
-
-
-
-
sclk
Typ
740
680
50
50
50
50
50
50
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1953
Max
108
216
108
216
54
60
20
32
54
60
55
20
60
55
20
60
55
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CS5381
DS563F2
Unit
kHz
kHz
kHz
kHz
kHz
kHz
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%
%
%
%
%
%
s
s

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