AD7738BRUZ Analog Devices Inc, AD7738BRUZ Datasheet - Page 4

• Manufacturer Part Number: AD7738BRUZ
• Description: IC ADC 24BIT 8-CH 28-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7738BRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 24
• Sampling Rate (per Second): 15.4k
• Number Of Converters: 1
• Power Dissipation (max): 100mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 24bit
• Input Channel Type: Single Ended
• Supply Voltage Range - Analogue: 4.75V To 5.25V
• Supply Voltage Range - Digital: 2.7V To 3.6V, 4.75V To 5.25V
• Sampling Rate: 15.437kSPS
• Rohs Compliant: Yes
• Number Of Elements: 1
• Resolution: 24Bit
• Architecture: Delta-Sigma
• Sample Rate: 3.05MSPS
• Input Polarity: Unipolar/Bipolar
• Input Type: Voltage
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 100mW
• Integral Nonlinearity Error: ±0.0015%FSR
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7738EBZ - BOARD EVAL FOR AD7738
• Lead Free Status / Rohs Status: Compliant

AD7738
TIMING SPECIFICATIONS
(AV
Parameter
MASTER CLOCK RANGE 1
READ OPERATION
WRITE OPERATION
NOTES
1
2
3
4
5
6
Specifications are subject to change without notice.
The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing
characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.
Sample tested during initial release to ensure compliance.
All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
See Figures 1 and 2.
These numbers are measured with the load circuit of Figure 3 and defined as the time required for the output to cross the V
This specification is relevant only if CS goes low while SCLK is low.
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 3.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DD
1
2
4
5
5A
6
7
8
9
11
12
13
14
15
16
4
6
4, 5
= 5 V
5%; DV
DD
= 2.7 V to 3.6 V or 5 V
Min
50
500
0
0
0
0
0
50
50
0
10
0
30
25
50
50
0
1, 2, 3
Typ
5%; Input Logic 0 = 0 V, Logic 1 = DV
Max
6.144
60
80
60
80
80
DD
) and timed from a voltage level of 1.6 V.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–4–
Test Conditions/Comment
SYNC Pulsewidth
RESET Pulsewidth
CS Falling Edge to SCLK Falling Edge Setup Time
SCLK Falling Edge to Data Valid Delay
DV
DV
CS Falling Edge to Data Valid Delay
DV
DV
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge after SCLK Rising Edge Hold Time
Bus Relinquish Time after SCLK Rising Edge
CS Falling Edge to SCLK Falling Edge Setup
Data Valid to SCLK Rising Edge Setup Time
Data Valid after SCLK Rising Edge Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge after SCLK Rising Edge Hold Time
DD
DD
DD
DD
of 4.75 V to 5.25 V
of 2.7 V to 3.3 V
of 4.75 V to 5.25 V
of 2.7 V to 3.3 V
DD
unless otherwise noted.)
OL
or V
OH
limits.
REV. 0