AD7738BRUZ Analog Devices Inc, AD7738BRUZ Datasheet - Page 22

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AD7738BRUZ

Manufacturer Part Number
AD7738BRUZ
Description
IC ADC 24BIT 8-CH 28-TSSOP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD7738BRUZ

Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Number Of Bits
24
Sampling Rate (per Second)
15.4k
Number Of Converters
1
Power Dissipation (max)
100mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
28-TSSOP (0.173", 4.40mm Width)
Resolution (bits)
24bit
Input Channel Type
Single Ended
Supply Voltage Range - Analogue
4.75V To 5.25V
Supply Voltage Range - Digital
2.7V To 3.6V, 4.75V To 5.25V
Sampling Rate
15.437kSPS
Rohs Compliant
Yes
Number Of Elements
1
Resolution
24Bit
Architecture
Delta-Sigma
Sample Rate
3.05MSPS
Input Polarity
Unipolar/Bipolar
Input Type
Voltage
Differential Input
Yes
Power Supply Requirement
Analog and Digital
Single Supply Voltage (typ)
5V
Single Supply Voltage (min)
4.75V
Single Supply Voltage (max)
5.25V
Dual Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Power Dissipation
100mW
Integral Nonlinearity Error
±0.0015%FSR
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
28
Package Type
TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-AD7738EBZ - BOARD EVAL FOR AD7738
Lead Free Status / Rohs Status
Compliant

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AD7738
Continuous Conversion Mode
When the Mode register is being written, the ADC Status Byte
is cleared and the RDY pin goes high regardless of its previous
state. When the continuous conversion command is written to
the Mode register, the ADC starts conversion on the channel
selected by the address of the Mode register.
After the conversion is complete, the relevant Channel Data
register and Channel Status register are updated, the relevant
RDY bit in the ADC Status register is set, and the AD7738
continues converting on the next enabled channel. The
AD7738 will cycle through all enabled channels until put
into another mode or reset. The cycle period will be the sum of
all enabled channels’ conversion times, set by corresponding
Channel Conversion Time registers.
The RDY bit is reset when the relevant Channel Data register is
being read. The behavior of the RDY pin depends on the
RDYFN bit in the I/O Port register. When RDYFN bit is 0, the
RDY pin goes low when any channel has unread data. When
this bit is set to 1 the RDY pin will only go low if all enabled
channels have unread data.
INTERFACE
INTERFACE
INTERFACE
SERIAL
SERIAL
SERIAL
RDY
RDY
RDY
CONTINUOUS
CONVERSION
CONTINUOUS
CONVERSION
CONTINUOUS
CONVERSION
START
START
START
CH0 CONVERSION
CH0 CONVERSION
CH0 CONVERSION
Figure 11. Continuous Conversion, CH0 and CH1, No Data Read
Figure 10. Continuous Conversion, CH0 and CH1, RDYFN = 1
Figure 9. Continuous Conversion, CH0 and CH1, RDYFN = 0
READ
DATA
CH0
CH1 CONVERSION
CH1 CONVERSION
CH1 CONVERSION
–22–
READ
READ
DATA
DATA
CH1
CH0
If an ADC conversion result has not been read before a new
ADC conversion is completed, then the new result will overwrite
the previous one. The relevant RDY bit goes low and the RDY
pin goes high for at least 163 MCLK cycles (~26.5 µs), indicating
when the Data register is updated and the previous conversion
data is lost.
If the Data register is being read as an ADC conversion completes,
then the Data Register will not be updated with the new result (to
avoid data corruption) and the new conversion data is lost.
Figure 9 shows the digital interface signals sequence for the
Continuous Conversion mode with Channels 0 and 1 enabled
and the RDYFN bit set to 0. The RDY pin goes low and the
Data Register is read after each conversion. Figure 10 shows a
similar sequence, but with the RDYFN bit set to 1. The RDY
pin goes low and the Data register is read after all conversions
are completed. Figure 11 shows the RDY pin when no data are
read from the AD7738.
CH0 CONVERSION
CH0 CONVERSION
CH0 CONVERSION
READ
DATA
CH1
READ
DATA
CH0
CH1 CONVERSION
CH1 CONVERSION
CH1 CONVERSION
READ
READ
DATA
DATA
CH0 CONVERSION
CH0 CONVERSION
CH1
CH0 CONVERSION
CH0
READ
DATA
CH1
REV. 0

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