CS5530-ISZ Cirrus Logic Inc, CS5530-ISZ Datasheet - Page 16

• Manufacturer Part Number: CS5530-ISZ
• Description: IC ADC 24BIT 1CH W/LNA 20SSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5530-ISZ

• Number Of Converters: 1
• Package / Case: 20-SSOP
• Number Of Bits: 24
• Sampling Rate (per Second): 3.84k
• Data Interface: Serial
• Power Dissipation (max): 45mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Architecture: Delta-Sigma
• Conversion Rate: 6.25 SPs to 3840 SPs
• Resolution: 24 bit
• Input Type: Voltage
• Interface Type: Serial (3-Wire)
• Voltage Reference: 2.5 V
• Maximum Power Dissipation: 500 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1158 - BOARD EVAL FOR CS5530
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1283-5

2.2.3 Serial Port Interface
The CS5530’s serial interface consists of four con-
trol lines: CS, SDI, SDO, SCLK. Figure 7 details
the command and data word timing.
CS, Chip Select, is the control line which enables
access to the serial port. If the CS pin is tied low,
the port can function as a three wire interface.
SDI, Serial Data In, is the data signal used to trans-
fer data to the converters.
SDO, Serial Data Out, is the data signal used to
transfer output data from the converters. The SDO
output will be held at high impedance any time CS
is at logic 1.
16
SCLK
SCLK
SCLK
SDO
SDO
SDI
SDI
SDI
CS
CS
CS
* td is the time it takes the ADC to perform a conversion. See the Single
Conversion and Continuous Conversion sections of the data sheet for more
details about conversion timing.
Command Time
8 SCLKs
Command Time
Command Time
8 SCLKs
8 SCLKs
Figure 7. Command and Data Word Timing
t *
d
MSB
MSB
Data Conversion Cycle
8 SCLKs Clear SDO Flag
Write Cycle
Read Cycle
SCLK, Serial Clock, is the serial bit-clock which
controls the shifting of data to or from the ADC’s
serial port. The CS pin must be held low (logic 0)
before SCLK transitions can be recognized by the
port logic. To accommodate optoisolators SCLK is
designed with a Schmitt-trigger input to allow an
optoisolator with slower rise and fall times to di-
rectly drive the pin. Additionally, SDO is capable
of sinking or sourcing up to 5 mA to directly drive
an optoisolator LED. SDO will have less than a 400
mV loss in the drive voltage when sinking or sourc-
ing 5 mA.
Data Time 32 SCLKs
Data Time 32 SCLKs
MSB
Data Time 32 SCLKs
MCLK
Clock Cycles
/OWR
LSB
CS5530
LSB
LSB
DS742F3