LTC1096CS8#PBF Linear Technology, LTC1096CS8#PBF Datasheet - Page 26

IC A/D CONV 8BIT SRL IN/OUT8SOIC

LTC1096CS8#PBF

Manufacturer Part Number
LTC1096CS8#PBF
Description
IC A/D CONV 8BIT SRL IN/OUT8SOIC
Manufacturer
Linear Technology
Datasheet

Specifications of LTC1096CS8#PBF

Number Of Bits
8
Sampling Rate (per Second)
33k
Data Interface
Serial
Number Of Converters
1
Power Dissipation (max)
600µW
Voltage Supply Source
Single Supply
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
Number Of Elements
1
Resolution
8Bit
Architecture
SAR
Sample Rate
33KSPS
Input Polarity
Unipolar
Input Type
Voltage
Rated Input Volt
5V
Differential Input
Yes
Power Supply Requirement
Single
Single Supply Voltage (typ)
5V
Single Supply Voltage (min)
3V
Single Supply Voltage (max)
9V
Dual Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Power Dissipation
500mW
Differential Linearity Error
±1LSB(Typ)
Integral Nonlinearity Error
±1LSB
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
8
Package Type
SOIC N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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LTC1096/LTC1096L
LTC1098/LTC1098L
TYPICAL APPLICATIONS
26
Hardware and Software Interface to Motorola MC68HC05C4
LOCATION A + 1
ANALOG
INPUTS
LOCATION A
MPU TRANSMIT
MPU RECEIVED
D
OUT
from LTC1098(L) Stored in MC68HC05C4
WORD
WORD
D
CLK
OUT
D
B7
CS
0
IN
LTC1098
B6
0
B5
0
D
CLK
OUT
D
CS
IN
B4
0
0
?
B3
0
0
?
Data Exchange Between LTC1098(L) and MC68HC05C4
B2
0
0
?
1ST TRANSFER
START
START
SCK
MISO
MOSI
C0
B1
BIT
0
MC68HC05C4
?
1
10968 TA05
SGL/
SGL/
DIFF
DIFF
B0
LSB
0
?
10968 TA04
ODD/
SIGN
BYTE 1
BYTE 2
ODD/
SIGN
?
BYTE 1
MSBF
MSBF
?
X
0
LABEL
START
X
B7
B7
MNEMONIC
BCLRn
LDA
STA
TST
BPL
LDA
STA
AND
STA
TST
BPL
BSETn
LDA
STA
B6
B6
X
DON'T CARE
B5
B5
X
BYTE 2 (DUMMY)
X = DON'T CARE
2ND TRANSFER
B4
B4
X
COMMENTS
Bit 0 Port C goes low (CS goes low)
Load LTC1098(L) D
Load LTC1098(L) D
Transfer begins.
Test status of SPIF
Loop to previous instruction if not done
with transfer
Load contents of SPI data register
into Acc. (D
Start next SPI cycle
Clear the fi rst D
Store in memory location A (MSBs)
Test status of SPIF
Loop to previous instruction if not done
with transfer
Set B0 of Port C (CS goes high)
Load contents of SPI data register into
Acc. (D
Store in memory location A + 1 (LSBs)
B3
B3
X
OUT
B2
B2
X
LSBs)
OUT
B1
B1
X
OUT
MSBs)
IN
IN
word
B0
B0
X
word into Acc.
word into SPI from Acc.
10968 TA03
10968fc

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