MCP3204-CI/ST Microchip Technology, MCP3204-CI/ST Datasheet - Page 22

• Manufacturer Part Number: MCP3204-CI/ST
• Description: IC ADC 12BIT 2.7V 4CH SPI14TSSOP
• Manufacturer: Microchip Technology

Specifications of MCP3204-CI/ST

• Data Interface: Serial, SPI™
• Number Of Bits: 12
• Sampling Rate (per Second): 100k
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 12bit
• Sampling Rate: 100kSPS
• Input Channel Type: Pseudo Differential, Single Ended
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Supply Current: 320µA
• Package: 14TSSOP
• Resolution: 12 Bit
• Architecture: SAR
• Number Of Adcs: 1
• Number Of Analog Inputs: 4|2
• Digital Interface Type: Serial (4-Wire, SPI)
• Input Type: Voltage
• Polarity Of Input Voltage: Unipolar
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MCP3204/3208
FIGURE 6-2:
6.2
When the MCP3204/3208 initiates the sample period,
charge is stored on the sample capacitor. When the
sample period is complete, the device converts one bit
for each clock that is received. It is important for the
user to note that a slow clock rate will allow charge to
bleed off the sample capacitor while the conversion is
taking place. At 85°C (worst case condition), the part
will maintain proper charge on the sample capacitor for
at least 1.2 ms after the sample period has ended. This
means that the time between the end of the sample
period and the time that all 12 data bits have been
clocked out must not exceed 1.2 ms (effective clock
frequency of 10 kHz). Failure to meet this criterion may
introduce linearity errors into the conversion outside
the rated specifications. It should be noted that during
the entire conversion cycle, the A/D converter does not
require a constant clock speed or duty cycle, as long as
all timing specifications are met.
DS21298E-page 22
MCU Transmitted Data
(Aligned with falling
edge of clock)
MCU Received Data
(Aligned with rising
edge of clock)
X = “Don’t Care” Bits
SCLK
D
D
OUT
CS
Maintaining Minimum Clock Speed
IN
MCU latches data from A/D converter
on rising edges of SCLK
0
1
?
Data stored into MCU receive
register after transmission of first
8 bits
0
SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).
2
?
0
3
?
0
HI-Z
4
?
0
5
?
Start
Start
Bit
1
6
?
Data is clocked out of A/D
converter on falling edges
SGL/
DIFF
SGL/
DIFF
7
?
D2
?
D2
8
D1
D1
9
?
Data stored into MCU receive
register after transmission of
second 8 bits
DO
DO
DO
10
?
X
11 12 13
?
NULL
BIT B11 B10 B9
X
(Null)
6.3
If the signal source for the A/D converter is not a low
impedance source, it will have to be buffered or inaccu-
rate conversion results may occur (see
also recommended that a filter be used to eliminate any
signals that may be aliased back into the conversion
results, as is illustrated in
is used to drive the analog input of the MCP3204/3208.
This amplifier provides a low impedance source for the
converter input, and a low pass filter, which eliminates
unwanted high frequency noise.
Low-pass (anti-aliasing) filters can be designed using
Microchip’s free interactive FilterLab
Lab will calculate capacitor and resistor values, as well
as determine the number of poles that are required for
the application. For more information on filtering
signals, see AN699, “Anti-Aliasing Analog Filters for
Data Acquisition Systems”.
0
X
B11 B10 B9 B8
X
14 15
Buffering/Filtering the Analog
Inputs
X
X
B8
16
Don’t Care
X
B7
17 18 19
B7 B6 B5 B4 B3 B2 B1 B0
Data stored into MCU receive
register after transmission of last
8 bits
X
© 2008 Microchip Technology Inc.
B6 B5 B4 B3 B2 B1 B0
Figure
X
X
20 21 22 23
6-3, where an op amp
X
®
X
software. Filter-
Figure
X
X
4-2). It is
24