MCP3204-CI/ST Microchip Technology, MCP3204-CI/ST Datasheet - Page 21

• Manufacturer Part Number: MCP3204-CI/ST
• Description: IC ADC 12BIT 2.7V 4CH SPI14TSSOP
• Manufacturer: Microchip Technology

Specifications of MCP3204-CI/ST

• Data Interface: Serial, SPI™
• Number Of Bits: 12
• Sampling Rate (per Second): 100k
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 12bit
• Sampling Rate: 100kSPS
• Input Channel Type: Pseudo Differential, Single Ended
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Supply Current: 320µA
• Package: 14TSSOP
• Resolution: 12 Bit
• Architecture: SAR
• Number Of Adcs: 1
• Number Of Analog Inputs: 4|2
• Digital Interface Type: Serial (4-Wire, SPI)
• Input Type: Voltage
• Polarity Of Input Voltage: Unipolar
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.0
6.1
With most microcontroller SPI ports, it is required to
send groups of eight bits. It is also required that the
microcontroller SPI port be configured to clock out data
on the falling edge of clock and latch data in on the
rising
MCP3204/3208 devices may not need multiples of
eight clocks, it will be necessary to provide more clocks
than are required. This is usually done by sending
‘leading zeros’ before the start bit. As an example,
Figure 6-1
3208 can be interfaced to a MCU with a hardware SPI
port.
Mode 0,0, which requires that the SCLK from the MCU
idles in the ‘low’ state, while
similar case of SPI Mode 1,1, where the clock idles in
the ‘high’ state.
FIGURE 6-1:
© 2008 Microchip Technology Inc.
X = “Don’t Care” Bits
MCU Transmitted Data
(Aligned with falling
edge of clock)
MCU Received Data
(Aligned with rising
edge of clock)
SCLK
D
OUT
D
CS
MCU latches data from A/D
converter on rising edges of SCLK
Figure 6-1
IN
edge.
APPLICATIONS INFORMATION
Using the MCP3204/3208 with
Microcontroller (MCU) SPI Ports
and
Figure 6-2
Because
depicts the operation shown in SPI
1
?
?
Data stored into MCU receive
register after transmission of first
8 bits
0
0
2
?
?
SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).
0
0
3
?
?
illustrate how the MCP3204/
communication
0
0
4
HI-Z
?
?
0
0
5
Figure 6-2
Data is clocked out of A/D
converter on falling edges
Start
?
?
0
0
6
Start
?
?
SGL/
DIFF
Bit
1
1
7
DIFF
SGL/
SGL/
DIFF
?
?
D2
8
shows the
?
?
with
D2
D2
D1
9
the
?
?
Data stored into MCU receive
register after transmission of
second 8 bits
D1
D1
DO
10
?
?
DO
DO
11 12 13 14 15 16
NULL
?
?
BIT B11 B10 B9 B8
X
X
(Null)
(Null)
0
0
As is shown in
the A/D converter contains five leading zeros before
the start bit. Arranging the leading zeros this way
allows the output 12 bits to fall in positions easily
manipulated by the MCU. The MSB is clocked out of
the A/D converter on the falling edge of clock number
12. Once the second eight clocks have been sent to the
device, the MCU’s receive buffer will contain three
unknown bits (the output is at high impedance for the
first two clocks), the null bit and the highest order four
bits of the conversion. Once the third byte has been
sent to the device, the receive register will contain the
lowest order eight bits of the conversion results.
Employing this method ensures simpler manipulation
of the converted data.
Figure 6-2
which requires that the clock idles in the high state. As
with mode 0,0, the A/D converter outputs data on the
falling edge of the clock and the MCU latches data from
the A/D converter in on the rising edge of the clock.
X
X
B11 B10 B9 B8
B11 B10 B9
X
X
X
X
shows the same thing in SPI Mode 1,1,
X
X
B8
Figure
X
X
X
MCP3204/3208
B7
Don’t Care
17 18 19 20
B7 B6 B5 B4 B3 B2 B1 B0
Don’t Care
B7
Data stored into MCU receive
register after transmission of last
8 bits
6-1, the first byte transmitted to
X
X
B6 B5 B4 B3 B2 B1 B0
B6
X
X
B5
X
X
B4
X
X
21 22 23 24
B3
DS21298E-page 21
X
X
B2
X
X
B1
23
B1
X
X
B0
X
X