AD73322LAR Analog Devices Inc, AD73322LAR Datasheet - Page 41

• Manufacturer Part Number: AD73322LAR
• Description: IC ANALOG FRONT END DUAL 28-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD73322LAR

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-SOIC (7.5mm Width)

CONFIGURING AN AD73322L TO OPERATE IN DATA MODE
This section describes the typical sequence of control words
that are required to be sent to an AD73322L to set it up for data
mode operation.
programmed before the device enters data mode. This
description refers to the steps in Table 27.
At each sampling event, a pair of SDOFS pulses is observed,
which causes a pair of control (programming) words to be sent
to the device from the DSP. Each pair of control words should
program a single register in each Channel. The sequence to be
followed is Channel 2 followed by Channel 1.
Step 1 shows the first output sample event following a device
reset. The SDOFS signal is raised on both channels
neously, which prepares the DSP Rx register to accept the ADC
word from Channel 2, while SDOFS from Channel 1 becomes
an SDIFS to Channel 2. As the SDOFS of Channel 2 is coupled
to the DSP’s TFS and RFS, and to the SDIFS of Channel 1, this
event also forces a new control word to be output from the DSP
Tx register to Channel 1.
Step 2 shows the status of the channels following the transmis-
sion of the first control word. The DSP has received the output
word from Channel 2, while Channel 2 has received the output
word from Channel 1. Channel 1 has received the control word
destined for Channel 2. At this stage, the SDOFS of both
channels are again raised because Channel 2 has received
Channel 1’s output word, and as it is not a valid control word
addressed to Channel 2, it is passed on to the DSP. Likewise,
Channel 1 has received a control word destined for Channel 2—
address field is not zero—and it decrements the address field of
the control word and passes it on.
Step 3 shows completion of the first series of control word
writes. The DSP has received both output words and each
channel has received a control word that addresses Control
Register B and sets the internal MCLK divider ratio to 1, SCLK
rate to DMCLK/2, and sampling rate to DMCLK/256. Both
channels are updated simultaneously because both receive the
addressed control word at the same time. This is an important
factor in cascaded operation as any latency between updating
the SCLK or DMCLK of channels can result in corrupted
operation. This does not happen in the case of an FSLB config-
uration, as shown here, but must be taken into account in a
nonFSLB configuration. Another observation of this sequence
is that the data-words are received and transmitted in reverse
order—that is, the ADC words are received by the DSP, Channel
2 first, then Channel 1 and, similarly, the transmit words from
the DSP are sent to Channel 2 first, then to Channel 1. This
ensures that all channels are updated at the same time.
Steps 4 to 6 are similar to Steps 1–3, but the user must program
Control Register C to power up the analog sections of the
device (ADCs, DACs, and reference).
1
In this sequence, Registers B, C, and A are
3
2
simulta-
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Steps 7 to 9 are similar to Steps 1 to 3, but the user must
program Control Register A, with a device count field equal
to two channels in cascade, and set the PGM/DATA bit to
one to put the channel in data mode.
By Step 10, the programming phase completed, and actual
channel data read and write can begin. The words loaded in the
serial registers of the two channels at the ADC sampling event
contain valid ADC data, and the words written to the channels
from the DSP’s Tx register are interpreted as DAC words. The
DSP Tx register contains the DAC word for Channel 2.
In Step 11, the first DAC word has been transmitted into the
cascade, and the ADC word from Channel 2 has been read from
the cascade. The DSP Tx register contains the DAC word for
Channel 1. Because the words being sent to the cascade are
being interpreted as 16-bit DAC words, the addressing scheme
changes from one where the address was embedded in the
transmitted word, to one where the serial port counts the SDIFS
pulses. When the number of SDIFS pulses received equals the
value in the channel count field of Control Register A—the
length of the cascade—each channel updates its DAC register
with the present word in its serial register.
In Step 11 each channel has received only one SDIFS pulse;
Channel 2 received one SDIFS from the SDOFS of Channel 1
when it sent its ADC word, and Channel 1 received one SDIFS
pulse when it received the DAC word for Channel 2 from the
DSP’s Tx register. Therefore, each channel raises its SDOFS line
to pass on the current word in its serial register, and each
channel receives another SDIFS pulse.
Step 12 shows the completion of an ADC read and DAC write
cycle. Following Step 11, each channel has received two SDIFS
pulses that equal the setting of the channel count field in
Control Register A. The DAC register in each channel is up-
dated with the contents of the word that accompanied the
SDIFS pulse that satisfied the channel count requirement. The
internal frame sync counter is reset to zero and begins counting
for the next DAC update cycle.
Steps 10–12 are repeated on each sampling event.
1
2
3
Channel 1 and Channel 2 refer to the two AFE sections of the AD73322L.
The AD73322L is configured as two channels in cascade. The internal
cascade connections between Channels 1 and 2 are detailed in
The connections SDI/SDIFS are inputs to Channel 1, while SDO/SDOFS are
outputs from Channel 2.
This sequence assumes that the DSP SPORT’s Rx and Tx interrupts are
enabled. Ensure that there is no latency (separation) between control words
in a cascade configuration. This is especially the case when programming
Control Registers A and B as they must be updated synchronously in each
channel.
AD73322L
Figure 23
.