AD73322LAR Analog Devices Inc, AD73322LAR Datasheet - Page 20

• Manufacturer Part Number: AD73322LAR
• Description: IC ANALOG FRONT END DUAL 28-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD73322LAR

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-SOIC (7.5mm Width)

AD73322L
DAC ADVANCE REGISTER
The loading of the DAC is internally synchronized with the
unloading of the ADC data in each sampling interval. The
default DAC load event happens one SCLK cycle before the
SDOFS flag is raised by the ADC data being ready. However,
this DAC load position can be advanced before this time by
modifying the contents of the DAC advance field in Control
Register E (CRE:0–4). The field is five bits wide, allowing
31 increments of weight 1/(F
Table 15. DAC Timing Control
DA4
0
0
0
1
1
Table 16. Control Register Map
Address (Binary)
000
001
010
011
100
101
110
111
Table 17. Control Word Description
15
C/D
Control
Bit 15
Bit 14
Bits 13 to 11
Bits 10 to 8
Bits 7 to 0
14
R/W
Frame
Control/Data
Read/Write
Register Address
Register Data
Device Address
DA3
0
0
0
1
1
13
S
Device Address
× 32), as shown in Table 15.
Name
CRA
CRB
CRC
CRD
CRE
CRF
CRG
CRH
12
Description
When set high, this bit signifies a control word in program or mixed program/data modes. When set
low, it signifies a data-word in mixed program/data mode or an invalid control word in program mode.
When set low, this bit tells the device that the data field is to be written to the register selected by the
register field setting, provided the address field is zero. When set high, it tells the device that the
selected register is to be written to the data field in the input serial register and that the new control
word is to be output from the device via the serial output.
This 3-bit field holds the address information. Only when this field is zero is a device selected. If the
address is not zero, it is decremented and the control word is passed out of the device via the serial
output.
This 3-bit field is used to select one of the eight control registers on the AD73322L.
This 8-bit field holds the data that is to be written to or read from the selected register provided the
address field is zero.
DA2
0
0
0
1
1
11
Control Register A
Control Register B
Control Register C
Control Register D
Control Register E
Control Register F
Control Register G
Control Register H
Description
10
DA1
0
0
1
1
1
Register Address
Rev. A | Page 20 of 48
9
The sample rate, f
divider and the sample rate divider, as shown in Table 12 and
Table 14. In certain circumstances this DAC update adjustment
can reduce the group delay when the ADC and DAC are used to
process data in series. For more information about how the
DAC advance register can be used, see the section Configuring
an AD73322L to Operate in Mixed Mode.
NOTE: The DAC advance register should not be changed while
the DAC section is powered up.
8
DA0
0
1
0
0
1
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
Width
8
8
8
8
8
8
8
8
S,
6
depends on the setting of both the MCLK
Time Advance
0 s
1/(F
2/(F
30/(F
31/(F
S
S
5
× 32) s
× 32) s
S
S
× 32) s
× 32) s
Register Data
Reset Setting (Hex)
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
4
3
2
1
0