DS1746-70 Maxim Integrated Products, DS1746-70 Datasheet
DS1746-70
Specifications of DS1746-70
Available stocks
Related parts for DS1746-70
DS1746-70 Summary of contents
Page 1
... V CC A16 Maxim 31 A15 2 DS1746 A14 N. A12 A13 A11 A10 DQ7 DQ6 DQ0 14 19 DQ1 DQ5 DQ2 15 18 DQ4 17 GND 16 DQ3 Encapsulated DIP 34 1 Maxim DS1746P GND BAT PowerCap Module Board (Uses DS9034PCX PowerCap N.C. N.C. A14 A13 A12 A11 A10 ...
Page 2
... V CC RST — 4 X1, X2, — V BAT DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs FUNCTION No Connection Address Input Data Input/Output Ground Active-Low Chip Enable Input Active-Low Output Enable Input Active-Low Write-Enable Input Power-Supply Input Active-Low Power-Fail Output, Open Drain. Requires a pullup resistor for proper operation. ...
Page 3
... ORDERING INFORMATION VOLTAGE PART RANGE (V) DS1746-70+ 5.0 DS1746-70IND+ 5.0 DS1746P-70+ 5.0 DS1746P-70IND+ 5.0 DS1746W-120+ 3.3 DS1746W-120IND+ 3.3 DS1746WP-120+ 3.3 DS1746WP-120IND+ 3.3 +Denotes a lead(Pb)-free/RoHS-compliant package. The top mark will include a “+” symbol on lead-free devices. *DS9034-PCX+ or DS9034I-PCX+ required (must be ordered separately). ...
Page 4
... CLOCK OPERATIONS—READING THE CLOCK While the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1746 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. ...
Page 5
... As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a one, like the read bit, halts updates to the DS1746 registers. The user can then load them with the correct day, date and time data in 24 hour BCD format. Resetting the write bit to a zero then transfers those values to the actual clock counters and allows normal operation to resume ...
Page 6
... WRITING DATA TO RAM OR CLOCK The DS1746 is in the write mode whenever WE, and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE, or CE. The addresses must be held valid throughout the cycle ...
Page 7
... The DS1746 has a lithium power source that is designed to provide energy for clock activity, and clock and RAM data retention when the V is sufficient to power the DS1746 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at 25C with the internal clock oscillator running in the absence of V power ...
Page 8
... Output Leakage Current (any output) Output Logic 1 Voltage (I = -1.0 mA) OUT Output Logic 0 Voltage (I = +2.1 mA) OUT Write Protection Voltage Battery Switchover Voltage DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs TEMP RANGE 0°C to +70°C, Noncondensing -40°C to +85°C, Noncondensing SYMBOL MIN TYP V 2 2.0 ...
Page 9
... AC CHARACTERISTICS—READ CYCLE (5V) = 5.0V 10 Over the Operating Range PARAMETER Read Cycle Time Address Access Time Low-Z CE Access Time CE Data Off Time Low-Z OE Access Time OE Data Off Time Output Hold from Address DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN TYP Icc Icc 1 Icc ...
Page 10
... Address Access Time Low-Z CE Access Time CE Data Off Time Low-Z OE Access Time OE Data Off Time Output Hold from Address READ CYCLE TIMING DIAGRAM A0-A16 CEA CE t CEL OE DQ0-DQ7 DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN t 120 CEL t CEA t CEZ t 5 OEL t ...
Page 11
... PARAMETER Write Cycle Time Address Setup Time WE Pulse Width CE Pulse Width CE and CE2 Pulse Width Data Setup Time Data Hold Time Data Hold Time WE Data Off Time Write Recovery Time Write Recovery Time DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN TYP ...
Page 12
... WRITE CYCLE TIMING DIAGRAM, WRITE-ENABLE CONTROLLED A0-A16 WEZ DQ0-DQ7 DATA OUTPUT WRITE CYCLE TIMING DIAGRAM, CHIP-ENABLE CONTROLLED A0-A16 DQ0-DQ7 DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs VALID t t WEW WR1 DH1 DATA INPUT t WC VALID t t CEW WR2 DH2 DATA INPUT ...
Page 13
... PARAMETER Before Power-Down V Fall Time PF(MAX) V PF(MIN) V Fall Time PF(MIN Rise Time PF(MIN) V PF(MAX) Power-Up Recover Time Expected Data-Retention Time (Oscillator ON) POWER-UP/DOWN TIMING (5V DEVICE) DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN TYP 300 REC MAX UNITS NOTES s s s s ...
Page 14
... PF(MIN) V Rise Time PF(MIN) V PF(MAX RST High PF Expected Data-Retention Time (Oscillator ON) POWER-UP/DOWN WAVEFORM TIMING (3.3V DEVICE) CAPACITANCE (T = +25°C) A PARAMETER Capacitance on All Input Pins Capacitance on All Output Pins DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN TYP 300 REC SYMBOL MIN TYP ...
Page 15
... Outputs are open. 4) Battery switchover occurs at the lower of either the battery terminal voltage Data-retention time is at +25C. 6) Each DS1746 has a built-in switch that disconnects the lithium source until V user. The expected t is defined for DIP modules and assembled PowerCap modules as a cumulative ...
Page 16
... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time 2010 Maxim Integrated Products DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs DESCRIPTION as specified by RAM vendors Maxim and the Dallas logo are registered trademarks of Maxim Integrated Products ...