X1226V8 Intersil, X1226V8 Datasheet
X1226V8
Specifications of X1226V8
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X1226V8 Summary of contents
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... All other trademarks mentioned are the property of their respective owners. X1226 4K (512 x 8), 2-Wire ™ RTC May 8, 2006 FN8098.3 Battery Time Switch Keeping Circuitry Registers (SRAM) Compare Alarm Regs (EEPROM) 4K EEPROM ARRAY | Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved BACK ...
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... X1226V8Z* (Note) 1226Z X1226V8I* 1226I X1226V8IZ* (Note) 1226IZ *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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PIN ASSIGNMENTS Pin Number SOIC TSSOP Symbol PHZ/IRQ SDA 6 8 SCL BACK X1226 Brief Description X1. The ...
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DESCRIPTION (continued) The Real-Time Clock keeps track of time with separate registers for Hours, Minutes, Seconds. The Calendar has separate registers for Date, Month, Year and Day-of-week. The calendar is correct through 2099, with automatic leap year correction. The powerful ...
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... For example, a >20ppm frequency deviation translates into an accuracy of >1 minute per month. These parameters are available from the crystal manufacturer. Intersil’s RTC family provides on-chip crystal capacitance to tune oscillator frequency from +116 ppm to -37 ppm when using a 12.5 pF load crystal. For more detail information see the Application section ...
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A read or write can begin at any address in the CCR not necessary to set the RWEL bit prior to writing ...
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ALARM REGISTERS There are two alarm registers whose contents mimic the contents of the RTC register, but add enable bits and exclude the 24 hour time selection bit. The enable bits specify which registers to use in the comparison between ...
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WEL: Write Enable Latch—Volatile The WEL bit controls the access to the CCR and mem- ory array during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is ...
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... The values calculated above are typical, and total load capacitance seen by the crystal will include approxi- mately 2pF of package and board capacitance in addi- tion to the ATR value. See Application Section and Intersil’s Application Note AN154 for more information. WRITING TO THE CLOCK/CONTROL REGISTERS Changing clock/control register requires the following steps: – ...
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SERIAL COMMUNICATION Interface Conventions The device supports a bidirectional bus oriented proto- col. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is ...
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Figure 4. Valid Start and Stop Conditions SCL SDA Figure 5. Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver Start DEVICE ADDRESSING Following a start condition, the master must output a Slave Address ...
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Figure 6. Slave Address, Word Address, and Data Bytes (64 Byte pages) Device Identifier Array CCR Write Operations Byte Write For a write operation, the device requires the Slave Address ...
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A write to a protected block of memory is ignored, but will still receive an acknowledge. At the end of the write command, the X1226 will not initiate an internal write cycle, and will continue to ACK commands. Page Write ...
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Acknowledge Polling Disabling of the inputs during nonvolatile write cycles can be used to take advantage of the typical 5mS write cycle time. Once the stop condition is issued to indi- cate the end of the master’s byte load operation, ...
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Random Read Random read operations allow the master to access any location in the X1226. Prior to issuing the Slave Address Byte with the R/W bit set to zero, the master must first perform a “dummy” write operation. The master ...
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ABSOLUTE MAXIMUM RATINGS Temperature Under Bias ................... -65°C to +135°C Storage Temperature ........................ -65°C to +150°C Voltage and PHZ/IRQ CC BACK pin (respect to ground) ............................-0.5V to 7.0V Voltage on SCL, SDA, X1 and X2 pin ...
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Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave Address Byte are incorrect or until 200nS after a stop ending a read or ...
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AC Specifications (T = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.) A Symbol f SCL Clock Frequency SCL t Pulse width Suppression Time at inputs IN t SCL LOW to SDA Data Out Valid AA t ...
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Write Cycle Timing SCL 8th Bit of Last Byte SDA Power-up Timing Symbol (1) t Time from Power-up to Read PUR (1) t Time from Power-up to Write PUW Notes: (1) Delays are measured from the time V V slew ...
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... In addition to the analog compensation afforded by the adjustable load capacitance, a digital compensation feature is available for the Intersil RTC family. There are three bits known as the Digital Trimming Register or DTR, and they operate by adding or skipping pulses in the clock signal. The range provided is ±30ppm in increments of 10ppm ...
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... RTC. Care needs to be taken in layout of the RTC circuit to avoid noise pickup. Below in Figure suggested layout for the X1226 or X1227 devices. Figure 15. Suggested Layout for Intersil RTC in SO-8 The X1 and X2 connections to the crystal are to be kept as short as possible. A thick ground trace around ...
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... Many types of batteries can be used with the Intersil RTC products. 3.0V or 3.6V Lithium batteries are appropriate, and sizes are available that can power a Intersil RTC device for years. Another option is to use a supercapacitor for applications where Vcc may disappear intermittently for short periods of time. ...
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Referring to Figure 16, Vtrip applies to the “Internal Vcc” node which powers the entire device. This means that if Vcc is powered down and the battery voltage at Vback is higher than the Vtrip voltage, then the entire chip ...
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Small Outline Package Family (SO PIN #1 I.D. MARK 0.010 SEATING PLANE 0.004 C 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...